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Comment by steve_musk | Hacker News Reader

What is the limit on creating bigger chips? If some of the money/effort was focused on being able to fab larger chips instead of decreasing feature size... I don't know much about lithography so maybe the answer is obvious to those that do.

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The "aperture size" in semiconductor manufacturing is a the practical limiting factor in chip size, and some chips (GPUs in particular) are already at the limit. It's basically the maximum size of the photolithography process (my understanding of semiconductor manufacturing is a bit weak).

Aperture size can be increased to some degree for future manufacturing nodes, but there's a limit to how practical it is.

Other factors also come into play. The distance light travels in a clock cycle has already been mentioned as a hard limit.

Cost is another matter: chips are rectangular but wafers are round. The larger the chips, the more there is wasted area the lower the yield per wafer. Intel has an advantage here, because they use 12" wafers when the rest of the industry uses 10" (this was a few years ago, things may have changed). Historically speaking, these wafers are huge compared to the 4" and 6" wafers of the past. Making the silicon ingots to cut the wafers from is another form of art, modern ingots are HUGE blobs of pure silicon.

I recommend paying a visit to Intel museum if you're around Silicon Valley. It's not a huge museum but has lots of interesting information, nice guides and a great photo-op to take a selfie with a big honkin' chunk of silicon (they've got full ingots and wafers on display).

Any reason why chips couldn't be hexagonal or triangular? Either one would still tile a wafer, and go closer to a round edge.

You can't start a saw in the middle of a wafer. You need to cut from end to end.

Triangles would work for that.

The area around the acute angles would be almost useless due to lack of routing space.

What about laser or a waterjet cutter?

AFAIK silicon has a crystalline structure which causes wafers to break on straight lines and at right angles. This might make things difficult for non-rectangular parts.

There's also a ton of practical issues regarding the process. Photolithography equipment, cutting the wafers, the machines handling and packaging the chips. All would have to be redesigned and I'm sure that would cost more than the saved silicon during the lifetime of the whole plant.

The current chip sizes are already getting pretty close to hard limits (speed of light, etc). 900 mm^2 is 30 mm across, which is about half of the distance light travels in a clock cycle (async/clockless circuitry could help here).

Larger chips are also less efficient. A while ago I was discussing power efficiency with a HW designer working on memory controllers and he was using a fancy unit called "nanojoules per bit-millimeter", ie. how much energy it takes to flip a bit that is physically located a certain distance away. The efficiency gets much worse as distance increases.

Increasing wafer size also improves the yield, which is why Intel has an advantage with 12" wafers (others have 10").

Instead of creating larger chips, the current trend seems to be about packaging more chips in a single package and connecting them more efficiently. In particular, it's about bringing memory closer to the CPU to get those bit-millimeters down.

Fwiw, electrical signals in global interconnects move at about half the speed of light. Near speed of light signaling techniques like transmission lines can be used, but aren't due to a variety of reasons.

Silicon wafers are much easier to manufacture in a circle shape.

Seems like most people here are bringing up speed of light problems, which are a concern, but it's not what stops you. The problem is that your yield goes down exponentially with die size, and binning them becomes a clusterfuck. The opposite direction of making smaller dies is fairly attractive though. For example, AMD split Threadripper into multiple dies on an MCM and seem to be saving a fortune on it, at the expense of some die area for interconnects. That way they can test and bin dies individually an assemble an MCM of known-good dies from the same bin.

I remember reading that GPUs are getting to fairly monsterous die sizes though - and they're paying for it.

Chips are fabb'd on a large wafer, which is then split up (see here: https://s3.amazonaws.com/ksr/assets/003/150/280/9b6a64c4d8ed... )

Now, the process isnt perfect, and you hear a lot about "yield" Which is basically how many chips on a wafer are not working to spec. Now, as you make a chip bigger, you increase the chance of a mistake. This reduces the "yield" and drives up the cost. (I'm not sure if its actually possible to make a full sized wafer without a mistake, I'll defer that to someone who knows)

In some cases those broken chips arn't all that bad, so they are shipped with the broken bits deactivated (This could be lies, but I think some AMD procs were done like this )

yes, there are other factors like propagation time, but thats solved by not having chip wide cache coherency.

> In some cases those broken chips arn't all that bad, so they are shipped with the broken bits deactivated (This could be lies, but I think some AMD procs were done like this )

That’s called “binning”

You don't increase the chance of a mistake, you increase the cost of a mistake because each little defect means you're throwing out a whole chip. The larger each chip is, the more expensive each little defect is.

Sony had a hard time when they were ramping up Cell processor production, so they designed the chips with 8 SPEs but only shipped them with 7 activated. That way if a defect happened to be in one of the SPEs, they could just turn it off and still ship the chip.

Say each platter has N defects spread uniformly. Double the area of each chip on the platter (less total chips) and you ~ double the defect rate per chip. Make the whole platter one chip and it always has a defect.

GPUs and CPUs somewhat work around it by being able to disable cores or a part of cache and sell the chip for less.

Perhaps it's time to resurrect wafer scale integration : https://en.wikipedia.org/wiki/Wafer-scale_integration

Which is used in the new Intel and AMD CPUs. IGPU on the same wafer. HBM for memory...

You've misunderstood. They put many chips inside one package, but the individual chips are still from different wafers.

Which is actually better as it means you can excise the faulty ones easily and/or fuse the broken subunits.

The main reason to integrate things is performance and it runs counter to yields.

If you can have a specialized process to produce whole wafers of HBM or GPU cores with decent yields then another good one to plug them together you have a winning combination.

Not understanding this is why the microprocessors from many subunits tended to fail badly. Either the design was not performant or it ran into yield issues or it has to use the exact same technology to integrate modules which was not invented or perfected at the time.

So you would need a process that does everything well which is much harder than having a specialized process plus integration.

Maybe it's a viable research project, but still far off from reality. The largest chips that can be manufactured with current technology are about 900 mm^2 in size, but a normal 10" wafer is about 51000 mm^2, which is 50x larger than the state of the art today.

An attempt to produce entire wafers in one go is also a big gamble. Any defects in the manufacturing could ruin the entire wafer rather than individual chips. Parts of the wafer could be disabled if defective, but it would result in a combinatorial explosion of different configurations.

Also worth noting that in 1980 when Wafer Scale Integration was researched (without success), wafers were 4" diameter. Current wafers are 10-12" in size, which makes the process much more difficult and error prone.

The two big waferscale efforts of the 1980s were by Gene Amdahl and Clive Sinclair.

Amdahl did run into technical problems connecting multiple wafers to build mainframes and using lasers to swap out bad subparts (both currently solved problems and normal industry practice).

But in Sinclair's case investors pulled out despite technical success because hard disk prices started falling exponentially after having stayed stable for many years. The irony was that he had done the "silicon disk" waferscale RAM just to not scare of investors with his real goal of a manycore processor on a wafer.

Cerebras is.

One problem with bigger chips is that the speed of light actually starts to be a problem. At 1 GHz one clock cycle is 1 ns which means that a light pulse in vacuum reaches maximum one foot in that time.

Cost of the wafer is fixed. The smaller the chip, the more chips per wafer, and thus, the cheaper each chip is.

Then add defects to that, which means you have to throw away more silicon per defect the bigger the chip.

IIRC it's about clock speed. Your electrical signals travel at the speed of light. If you have a 4GHz clock the signal travels at 300,000,000 m/s. Now one clock cycle is 0.00000000025s, so the light has time to travel 0.075m. That's only 7.5cm! And you need everything to be synchronized inside and get into a steady state before the next clock cycle.

Electrical signals don't travel at the speed of light, but your argument is still valid.

Actually, they very nearly do.

    The speed of electricity in a 12-gauge copper wire is
    299,792,458 meters per second x 0.951 or 285,102,627
    meters per second. This is about 280,000,000 meters
    per second which is not very much different from the
    speed of electromagnetic waves (light) in vacuum.

Not wires across silicon, which have higher capacitance and much higher resistance. For millimeter-long connections you might get 1/10 of C, ie 33 ps/mm instead of 3.3.

Hey, that's actually really interesting, thanks for the followup!

This corroborates what you're saying:

https://www.reddit.com/r/askscience/comments/204hl2/at_what_...

Transmission line signalling can get near speed of light in silicon. But it has its own issues :)

The synchronization can be avoided somewhat by the use of (also power efficient) asynchronous electronics. You can also employ lower frequency clock them multiply it on site. A bit more cost because now you have to handle clock jitter.

And then we have computing separated by meters of wire and network fabrics in clusters.

So size is not that much of a problem. It is just that free lunch for programmers has ended some 10 years ago.

The reticle limit of 193i immersion steppers is ~33x26mm which means to go larger you need multiple exposures to cross them. This is very slow, expensive and terrible for yield.

Bigger processors means longer distances for current to travel, thus longer delays, and therefore lower possible clock frequencies.

Not at all. In modern many-core chips, latency and complexity are already mitigated by having cores talk to only their neighbors. A meter-wide version would run at the same clock speed, if you could make it.

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