My implicit point was that addressable memory size is
not a factor when choosing between 32 and 64-bit ARM.
Looks like I should have communicated it more clearly.
AArch64 does have some perks, but mostly for out-of-order cores, which RPI3's Cortex A53 is not.
That said, even A53 can benefit from 31 registers in 64-bit mode. Large virtual address space is nice not only for memory mapping files, but to do lazy initialization while keeping high performance direct pointer access characteristics. That way you can have the MMU doing the check and indirection for you instead of slow explicit conditional check in code.
You can mitigate pointer size by ensuring memory accesses are PC-relative. Perhaps there could be support for something similar to x32 ABI [0] as well.
AArch64 codegen does need to generate more conditional jumps or CSELs (like cmove) though. Also function entry & exit code is larger due to lack of LDM & STM (load/store multiple). But on the other hand, stack spills are rarer, thanks to 31 general purpose registers instead of 14 on 32-bit ARM.
Where AArch64 truly shines is when you have a real out-of-order CPU core, for example Cortex A72. There are significantly more opportunities for instruction level parallelism due to dropping instruction predicates and other changes.
[0]: https://en.wikipedia.org/wiki/X32_ABI