You should be thinking in terms of state machines, pipelines, routing, delay & setup+hold constraints.
HDLs are just a high-powered blueprint languages. At the end of the day you're still just laying out physical blocks.
You should be thinking in terms of state machines, pipelines, routing, delay & setup+hold constraints.
HDLs are just a high-powered blueprint languages. At the end of the day you're still just laying out physical blocks.
I am not talking out of thin air and wild guesses how things should be, rather about my personal experience how we learned digital circuit design and how later, already with that skill, we applied the ideas to FP.
That was the goal of my initial comment, Hardware Design Ideas -> Help understating FP function combinations as if they were ICs, not how to design hardware from FP concepts.
You can't capture pipeline depth, SRAM usage, thermal envelope/clock gating that have significant real world impacts on your design.