Correct me if I'm misunderstanding something, but won't this chip need a ton of ADCs to process these computations?
2. CDAC + switched capacitor multiplier + SAR ADC can be competitive with digital multiplier.
2. Switched capacitor multipliers (actually almost anything analog) have difficulty scaling with feature shrinks, and that's before considering noise. E.g. see all the difficulties Xilinx went through to get 16nm FinFET ADCs efficiently working.