Mmap’d IO is still a shit show because of clearing the CR3 register on page faults.
Needs to be done on Intel CPUs older than Haswell, on those CPUs without INVPCID support.
With INVPCID you can partially invalidate TLB.
From 4.14 on, Linux has used PCID to improve context switches, independently of PTI. While writing that code, I did a bunch of benchmarking. INVPCID is not terribly useful, even with PCID. In fact, Linux only uses INVPCID on user pages to assist with a PTI corner case. It's not entirely clear to me what Intel had in mind when INVPCID was added
They're slower, because kernel needs to be mapped in and out of virtual address space, just like for syscalls.
If the access pattern is sufficiently local, perhaps this could be mitigated by using large (2MB) pages. A bad idea for a random access pattern, of course.