I guess I'd like to see much tighter integration between the two chips so that we don't have to write code that avoids the PCI bus at all costs. Today you fit your entire working set into VRAM and don't touch it from the CPU, so it's sort of hard to say "it's not a deal we don't saturate the bus anyway" when that's only because we bend over backwards to not touch the bus in the first place.
Isn't that the kind of optimizations that you can only make for consoles, where you know that all users have the same hardware?
No, modern GPU APIs give you plenty of control over data layout, and it's the model AMD had been pimping for a while with their 'HSA' push.
I wasn't thinking about technical constraints, but economic ones. The market that would be able to benefit from this kind of optimization would be very limited as a % of PC gamers (which is already a limited market compared to consoles AFAIK).
I would imagine that they took the best GPU chip they could afford the space and power for, and found that 8 channels was enough for 99% of their customers?
I assume adding more channels takes space, perhaps the GPU would have had to be lower performance to add more channels?
(speculating)
It's not like they had an option, NVIDIA doesn't do semi-customs you either buy their SOCs or their GPUs as a package.
Could you elaborate what you mean by tighter? Isn't this the whole point MCM designs?
Right, exactly, but this chip is still as far away from a software perspective as a discrete card would be.