EUV Lithography Finally Ready for Chip Manufacturing | Hacker News Reader

EUV Lithography Finally Ready for Chip Manufacturing

spectrum.ieee.org

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Really curious, how can - from a signal processing perspective - 100 applications of a 193 nm wave, come to define 7 nm features? This can't be additive, is there some form of modulation going on on the surface of the silicon? Anyone know?

Nothing in 7nm is actually 7nm in size same goes for all other nodes.

That said patterning and interference is used to create subwavelengnt features.

Interference of a 193nm wave can only yield a 193nm wave, it being additive. I'm curious what is done to get to 7nm.

Could a subtractive mechanism work? For example, if you want to create a 5nm bump, but you only have a 20nm thick tool to draw bumps, you could draw "everything except the 5nm bump".

In other words, draw a 20nm thick annulus around a 5nm center, thereby having achieved the desired result: drawing a 5nm object with a 20nm tool.

That's a toy example, idk quite how that would translate to photolithography.

They do something like this with sidewall patterning: https://en.wikipedia.org/wiki/Spacer_patterning

It’s not a one off etch it’s a series of etchings and depositions of material over the surface until you get the final product.

Self aligning quadruple patterning

https://blog.lamresearch.com/wp-content/uploads/2015/12/Self...

https://youtu.be/d5uoklMx63I

As I said nothin actually goes down to 7nm but they use multiple patterning basically the exposure or lack there off can be much finer than the wavelength of the light because they expose it multiple times through slightly different patterning.

Also ICs are made hang both subtractive and additive processes basically a series of exposures etches and depositions which at the end create the final product.

To put it simply if you have a 5mm mill you can still make a <5 mm feature by milling around say a 1mm square.

ELI5 why is the multiple patterning not additive in the same way as interference?

You’re not taking the resist mask into account, or multiple passes. https://en.m.wikipedia.org/wiki/Multiple_patterning

Not sure how to ELI5 it though...

I have no idea really, but the above explanation implies reminds me on the double slit experiments. Also, inference is additive in the amplitude, but phase shifts much smaller than the wavelengths are used in interferometers to measure layer depths.

https://en.wikipedia.org/wiki/Double-slit_experiment

https://en.wikipedia.org/wiki/List_of_types_of_interferomete...

I believe it’s mostly single slit and diffraction, light can pass through holes smaller than its wavelength but even that isn’t needed just yet, nanophotonics will be the next step tho.

http://web.eecs.utk.edu/~jaynewu/Teaching/resolution.pdf

Forget the patterning and interference for a second.

The process isn’t a one off resist mask and etches you have a series of expose, etch and disposition passes over the material.

The actual feature size can be made much smaller because it can be the product of multiple exposures, etches and depositions.

So let’s say that the smallest feature size you have from a single mask is 200nm by using multiple masks and exposure you basically can build small features which are defined by the overlapping lit or shadow areas of the mask.

These features can also be ethched in a controlled manner to create even finer feature size.

To simplify it even further take make a shadow of an open palm with fingers fully extended so the gap between the fingers is the largest as you can make it and make an outline of the lit areas, now shift your hand slightly to the left or the right and make an outline of the shadowed area and subtract that from the previous outline it's now smaller without you having to change the size of your pattern or the wavelength of the light.

The pattern still is constrained by the wavelength.

What is not constrained by wavelength is deposition and etching of layers, that could be (in theory at least) as thin as you like down to a monolayer.

With multipatterning you can place such small features, but the layout still is constrained by the wavelength.

Multipatterning. With cleverly designed masks, you can use the etching of a coarser layer to create finer patterns out of essentially "residuals" left behind. Repeat this process for finer and finer patterns, with error being compounded on each step. This is what the article means when they say a wafer makes 15 trips to the litho machine. With EUV, you would still need multipatterning, but less steps, which is cheaper and less error prone.

Besides multipatterning, there's also immersion photolithography. By using a liquid with an index of refraction higher than air/vacuum, you can shrink the wavelength. With an index of refraction of 2, something with a vacuum wavelength of, say, 300nm becomes 150nm. That, combined with multipatterning, can help further reduce the feature size.

I think that immersion photolithography doesn't work too well with extreme UV because there aren't many liquids which are transparent in this region.

EDIT: to use water as an example, you can see here why 193nm is basically the limit for the technique of immersion photolithography. The absorption spectrum is extremely steep at 193nm, so at shorter wavelengths, essentially no light gets through: http://www1.lsbu.ac.uk/water/images/water_spectrum_2.gif

Inverse Lithography

http://nanocad.ee.ucla.edu/pub/Main/SnippetTutorial/ILT.pdf

https://semiengineering.com/what-happened-to-inverse-lithogr...

There are all sorts of techniques you can use to create features smaller than the wavelength. Optical Proximity Correction, Immersion, phase-shifting, multi-patterning, etc:

https://en.wikipedia.org/wiki/Immersion_lithography

https://en.wikipedia.org/wiki/Optical_proximity_correction

https://en.wikipedia.org/wiki/Phase-shift_mask

https://en.wikipedia.org/wiki/Multiple_patterning

There are still some pieces that need to come together on this https://semiengineering.com/issues-and-tradeoffs-for-euv/ and https://semiengineering.com/unsolved-litho-issues-at-7nm/

>EUV Lithography Finally Ready for Chip Manufacturing

I have heard it every year, for the past 10 years

This is the first time I've heard of a 250W 19nm laser. That's a huge step forward.

The article mentions 13.5nm. Is 19nm the wavelength used to blast the tin that re-emits as the the 13.5nm EUV source? Is that where the power is going to result in a few watts at the printing surface?

First question, no, they use CO2 lasers which emit in the um range, not nm. Probably a typo.

Second question, the loss of power is due to two factors: 1) Conversion efficiency of CO2 laser pulse to EUV light pulse. This is in the single digit range as a percentage. 2) Transmission loss of EUV from light source to wafer. EUV mirrors reflect in the ballpark of 50% of the light, and there are many of them inside the scanner, so you have .5 * .5 * .5...

Very true, but according to the article chip makers are actually planning to use it in production this year. And they've actually started ordering more EUV systems, which is another sign it might be for real this time: http://www.electronicdesign.com/embedded-revolution/asml-ord...

If TSMC is getting 21E9 transistors on a 12 nm process (i.e. Nvidia Volta), then I assume a 1 nm process would be almost 3E12 transistors. That's insane!

Unless power dissipation drops 144x, I can't see that happening, unless it's for memory applications. Crazy to think about though.

Dennard scaling is what would allow that to happen. Unfortunately, the lesser known cousin of Moore's Law is essentially dead.

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