The verilog it generates, however, is on the edge of readable, which makes it a problem if you need to debug something using waveforms.

I tried to make a verilog DSL in julia, which was a lot of fun, but I got stuck on how to implement sequential logic (instead of just combinatorial logic). Even better (and should be reasonably doable with clever application of julia's macro and type system) would be to take a julia function and transparently generate verilog from it.