Leveraging RISC-V for AI and Machine Learning | Hacker News Reader

Leveraging RISC-V for AI and Machine Learning

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61 pointsrbanffy10 comments

Nice that RISC-V is in the news.

For those who follow RISC-V, this doesn't add any new information that wasn't already made public during the latest RISC-V conference. Proceedings here: https://riscv.org/2017/12/7th-risc-v-workshop-proceedings/

I wonder how Esperanto compares to Green Arrays [1] or REX [2]. Obviously, these are very different approaches and GA doesn't even support float. But REX does.

http://www.greenarraychips.com/home/products/

http://rexcomputing.com/

Is Rex Computing still in business? Just yesterday I was thinking about the founder who had won the Theil prize. I don't think their website has any updates.

I'm very curious about Green Arrays, but at US$450 for a dev board, it's beyond my threshold for weekend projects.

It'd interesting to explore how Arduino and, later, the RPi impacted their respective architectures' presence in the embedded space.

Don't know much about Green Arrays. It seems slightly strange in that most tasks that can make use of massive data parallelism are FP-heavy (numerical simulations, ML/AI).

As for REX, I don't really know what to think about it. Here's a recent thread on RWT: https://www.realworldtech.com/forum/?threadid=172976&curpost... . People there seem quite skeptical about the whole thing.

For a relatively new design, the GreenArrays chip is highly unusual:

1) Asynchronous logic. 2) Stack machine design. 3) Extremely limited memory per cell. 4) 18-bit words. 5) No MMU.

Chuck Moore gave a nice presentation on applications and his rationale here: https://www.infoq.com/presentations/power-144-chip

I thought it was pretty neat how in some of his design docs, a column of async cores are used as a memory controller.

I'm not sure about REX, but Esperanto is pretty far away from greenarrays. From what I got out of their talk at the latest Risc-V workshop[3] (video[1], slides[2]), they're going for the big high-performance end of the spectrum. The chip they were talking about is supposed to have 16 64-bit OoO Risc-V cores and 4096 RV64GC cores with vector units connected by some sort of network on chip.

[1] https://www.youtube.com/watch?v=f-b4QOzMyfU

[2] https://content.riscv.org/wp-content/uploads/2017/12/Tue1136...

[3] https://riscv.org/2017/12/7th-risc-v-workshop-proceedings/

The Esperanto presentation video from the recent risc-v conference:

https://www.youtube.com/watch?v=f-b4QOzMyfU

Was this title generated by a markov model of other HN titles?

clearly not, it is missing "blockchain" somewhere in the title

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