Esperanto Technologies to develop energy-efficient chips on RISC-V | Hacker News Reader

Esperanto Technologies to develop energy-efficient chips on RISC-V

embedded-computing.com

65 pointsdeepnotderp16 comments

"Unstealths": announces that it plans to develop...

Right, this seems to be an announcement of a possible forthcoming announcement. A more substantive story would be a better fit.

The thing is that it doesn’t matter how many cores you have if they cannot communicate with each other, memory, and IO with performance and relative ease of programmability. Supporting this many cores requires a network-on-chip which adds latency and complexity to all operations where a core must access resources outside of itself.

There is no way that these things could achieve reasonable throughput without a particularly convinient workload and very low level programming. Systolic matrix multiplication on a array of cores connected in a toroidal network-on-chip for example (see Adaptive’s chips).

There is no way that this thing has cache coherency. If your lucky it might have some hardware mailbox/mutex/semaphore to help keep all the cores in sync.

Really if you want this many ALUs gang them together into a vector machine like a GPU!

Anyway, all just speculation; there’s no substantiative details on the announcement or their site.

Not that I don’t want to see new and interesting things in computer hardware; I do! I just think that iterating away on the RISC is not the way to make leaps and bounds.

I thought there was a breakthrough a while ago about syncing cores with low latency?

Message passing.

It sounds like this basically is a GPU (complete with a "we didn't learn from Larrabee" software renderer).

In my head, CPU's have few cores (1-16) but those cores are very highly optimized and have lots of specialized hardware in them. In comparison, GPU's have many cores (thousands) that are comparatively dumber, but that's fine because we use GPU's when we want to run lots of simple operations in parallel, like image processing, etc.

With that in mind, where does this chip fit into the current space? Is it meant to replace both? It contains their two different kinds of cores, which I'm assuming are similar to the complex cores we have in CPU's and the simple cores we have in GPU's. Does this mean that if chips like this are used in the future, we wouldn't have separate processing units?

Also, how does one use an SoC like this? What are its inputs and outputs? How do I access those? Do I need specialized hardware? Can I plug it into my existing desktop? Do they expect a new system to be built around this, or is it a drop in replacement for a part in an existing system?

And in the same vein, does this encroach on some use cases for FPGA?

Surely even with parallel programming being notoriously hard to get right it's most probably easier than FPGA programming.

Once you get above a few cores, the only way to feasibly utilize them is to have data parallelism. And when you need to exploit data parallelism, programming models change and data bandwidth (both in interconnect between CPUs and to/from memory) becomes the limiting factor rather than compute bandwidth.

The only way to fit in a large number of cores on a die is to slim down the cores to remove space-hungry stuff (e.g., out-of-order). This makes the cores weak for single-threaded stuff, which means you're generally firmly in the HPC market and not suitable for personal use. It also requires pretty much developing different programming models, at which point the value-add compared to, say, a GPU seems hard to find. Note that one of the key points of the GPU model is that it oversubscribes the processors with work and swaps threads in and out while they're waiting for memory to complete, something like 16-way SMT.

I'll note that Intel did build something like this (the Xeon Phi), but they appear to be dropping it.

The GPU has many cores but they are organised in groups that share the instruction cache and decode logic, so they all execute the same program in lock-step (AMD call these 'wavefronts' and NVIDIA call this 'warps').

A many-core RISC-V has many independent cores, all with running their own cache and decode logic so all able to run different code and stall independently of each other.

There are problems beyond graphics where warps or wavefronts are great matches, and for those problems GPGPUs are very effective. But there are also problems where, even if each core is basically running the same program, cores can diverge and for that you want cores with their own decoders so they can stall or branch independently.

Its all a tradeoff.

>. In comparison, GPU's have many cores (thousands) that are comparatively dumber, but that's fine because we use GPU's when we want to run lots of simple operations in parallel, like image processing, etc.

They don't have that many cores. Look at AMD's Vega 64. It's right in the name. It has 64 cores. Each core is very dumb but also very big with 64 ALUs.

The article makes it clear they are unveiling/announcing their plan/intent to develop this chip design. Follow the links to their website and it feels like they are so far from “ready” it hurts.

TLDR: They are just getting PR for their not yet developed hardware designs, and they haven’t even explained who will be buying them.

We used to use the term “Vaporware”

Dave Ditzel is no slouch. I'll be interested in seeing how this goes.

Yup: CRISP, Sparc, low power x86 (Transmeta) and now high performance RISC-V. Business decisions (such as Lucent dropping out of the processor market or IBM killing its bulk CMOS fab) have kept his technical achievements from getting the commercial success they deserve. I hope things go better this time.

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