Intel vs. NuFlare in multi-beam race
semiengineering.com
semiengineering.com
In any case,
> how long it takes to write a mask is the principal determination of both the cost of the mask and also the yield of the mask
Masks are "written" on the silicon in layers and then etched out, most IC manufacturing processes use multi-patterning which means that multiple masks are printed on the silicon, exposed and then etched out.
The longer it takes to make an IC the lower the yields which bring up costs considerably.
Edit: well I was partially incorrect Photomasks are still used maskless manufacturing aka MAGIC isn’t there yet a combination of hard masks which are printed on the silicon and Photomasks are used to create the pattern.
Intel currently uses quadruple patterning so 4 masks in total are needed to create the final pattern.
There is a bit more complexity for 2.5 designs such as wall masking but this is beyond me.
No, you were completely incorrect TBH.
Today we do use 2.5D transistors AKA FinFets but that's still as single layer.
Multiple masks are used however as creating the feature size expected today with the wavelengths we have requires multiple patterning which means multiple masks are used.
14nm today still uses the same 193nm lithography from 65nm if not earlier, the only way to create features which are actually smaller than the wavelength of the light is by using multiple hard mask and resist layers.