Transport-Triggered Architectures

tce.cs.tut.fi

30 pointsakakievich5 comments

This is very interesting but does not appear to be helpful for the development of my TTA processor design. It appears that this project aims for more parallelism similar to VLIW than my simple MOVE architecture targets.

I would very much appreciate feedback and suggestions regarding my preliminary specifications which will be changing in the near future (before year's end) to include MUL, DIV, and floating point support. I really want to have a firm specification before proceeding with the VHDL implementation.

You can view what I have done at https://github.com/BillBohan/NISC .

Which of course, sounds awesome. Are there any implementations/examples we can check out? Does this relate to the concept of a "systolic array" in some way?

sorry, i should have seen the wikipedia link and it's citations.

regardless, is there any open-source hdl code for a platform-capable implementation basis?

it certainly seems like a great way to achieve ASIPs and extensibility as the big-little and heterogenous folks aim for.

I know the Maxim MaxQ is a microcontroller that implements a transport triggered architecture.

Maxim seems to have quietly EOL'd most if not all of them.

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