Rv8: a high performance RISC-V to x86 binary translator [pdf] | Hacker News Reader

Rv8: a high performance RISC-V to x86 binary translator [pdf]

carrv.github.io

71 pointsingve20 comments

But...why? X86 to riscv could at least be claimed to be useful (run legacy soft). There is ZERO riscv software at all (and thus zero closed source riscv software).

From the introduction:

Given Intel’s and AMD’s access to the latest process nodes, 4+ GHz clock speeds, superscalar execution, several dozen cores and hundreds of GB of memory in a server, a near native speed RISC-V binary translator is likely to be the fastest RISC-V implementation and most practical build environment for things such as operating system distributions for some years to come.

Any particular reason why build environments cannot rely on cross compilation for producing OS distributions?

They can, but this is more universal.

Also, I could see an argument for it if your build includes automated testing and you want to run your actual binaries (albeit via emulation) in those tests.

That also explains why nobody should spend time making riscv software right now - no chance of competitive speeds with Intel/AMD.

I believe it is competing initially with ARM. There are already RISC-V chips that are competitive with Cortex M4 and similar.

Well, there are designs that claim to be. They are neither ordereable in quantities of 100,000+ nor do they include any peripherals or even built-in flash.

That’s a it of a chicken egg problem. Also with ARM64, Linux distributons in the beginning had problems finding fitting server hardware for their build servers.

> There is ZERO riscv software at all

Exactly. So if you are porting your code to RISC-V don't you want as fast of a simulator as possible?

There's a link yesterday about xbox360 emulation on PC. Xbox360 and PlayStation 3 use Risc, so... there's that software.

Those were both (more or less) the IBM's Power ISA, not RISC-V.

> There is ZERO riscv software at all

Really? If you mean software for the RISC-V/x86 emulation you are possibly right. Regarding RISC-V in general however your statement is not true.

Fabrice Bellard has published a working Linux on 32/64 bit RISC-V [1]. There is no reason that we could not expect Linux to run on real RISC-V hardware next year on a SiFive Quadcore.

[1] https://bellard.org/jslinux/

Anyone know of a similar binary translator for RISC-V to ARM?

Compile RISC-V QEMU or RISC-V Spike simulator on ARM?

if only it wasn't that expensive to get a license for x86

x86 isn't that good. RISC-V has similar code density as amd64 while being fairly simpler. There's not much appeal to x86 as an ISA, other than for running legacy software.

running 'legacy software' is for most use cases probably the most important feature.

Most "legacy software" can be rebuilt from source code. For software where the sources aren't available, there's only a small subset where performance is the main priority. The rest can be handled through emulation.

The last time I checked, the patents have expired on anything pre-Pentium, and by now the Pentium patents probably have expired too.

I am aiming for the expiration of Intel patents for stuff up to SSE2, which will likely happen in the next few years.

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