RISC-V based 64-bit quad-core application processor | Hacker News Reader

RISC-V based 64-bit quad-core application processor

sifive.com

255 pointswanderingjew77 comments

I'm quite excited about Risc-V as a platform - particularly security and trust-wise. It's great to see that we'll be getting competitive CPUs soon.

Open hardware, implementing an open architecture, which can run open source software with reproducible builds. A huge win when we're facing pervasive surveillance hard-wired into current commodity systems.

> particularly security and trust-wise

Towards that end, has there been work on a TileLink IOMMU yet?

Open hardware? Open architecture? SiFive's solution is neither of those.

Okay, one of you is getting downvoted, but I'm not sure which one, yet.

The SiFive coreplexes themselves are based on the UCB-BAR Rocket core generator, which is open source. Most of the SiFive founders worked and still contribute to Rocket.

I wish I could share your optimism :/ Nothing stops makers of RISC-V SoCs from adding their own Intel ME equivalents. Also, the CPU is just a small part of a computer, so "RISC-V" doesn't automatically translate to "open hardware" or "open architecture".

> Also, the CPU is just a small part of a computer, so "RISC-V" doesn't automatically translate to "open hardware" or "open architecture".

It is a prerequisite to it though.

update: Also, they already have something acting in the role of the ME on this machine, marked E51 on the chart. I don't think it does the high level application type stuff that the ME does, but I would think it handles power management and other core duties of the ME.

it's owner-programmable, which is a plus.

Security and trust-wise RISC-V means nothing.

RISC-V is just open instruction set. Below the instruction set is microarchitecture.

Some have developed low performance free microarchitectures for Risc-V but same applies to other instruction sets also. You can develop open and secure X86 microarchitecture if you want.

High performance microarchitecture costs hundreds of millions of dollars to develop. Someone may develop competitive RISC-V CPU someday but it will not have open microarchitecture. AMD and Nvidia are examples of fabless companies who develop and sell proprietary microarchitectures. Thinking that someone develops open platform that competes with them is not realistic.

SiFive Coreplex IP is good for microcontrollers and alike and relatively transparent but there are similar microcontroller cores available from ARM with similar transparency.

> You can develop open and secure X86 microarchitecture if you want.

Apparently there are patent landmines you have to traverse first.

And those landmines even blew up in Nvidia's face.

Instruction set can't be patented. Intel tries to patent ways to implement and functions those instructions carry.

RISC-V will have less problems with those kind of patents, but it's impossible to design high-end microarchitecture without cross-licensing.

I may sound negative, but I'm actually positive about RISC-V in embedded and IoT arena. People just attach too much hype for the architecture.

> Instruction set can't be patented. Intel tries to patent ways to implement and functions those instructions carry.

ionno, try telling that to Microsoft. This wasn't welcoming: https://arstechnica.com/information-technology/2017/06/intel...

> Instruction set can't be pantented

This is simply false, as far as Intel is concerned. You can't even emulate x86 (therefore infringing 0 hardware patents) without expected heavy litigation from Intel.

AFAIK the actual x86 patents have expired but none of the extensions have (x86-64, SSE, ...)

Intel naturally tries to threaten and extend patents as much as they can. But they ISA itself can't be patented.

If you look their actual patents, they are all patents on implementation details or attempts to patent functions that instructions do.

> "Intel naturally tries to threaten and extend patents as much as they can. But they ISA itself can't be patented."

It is practically impossible to implement these extensions, such as SSE variants, without intel being able to make a case against you. So even if theoretically the ISA can't be patented, for all practical purposes they have the legal power to effectively prohibit a 3rd-party from implementing an x86 core.

x86-64 is AMD's IP, not Intel's. The proper name is AMD64.

"AMD64" is simply a Trade Mark. But the problem being discussed is the separate IP issue of patents.

Intel owns patents on the Itanium ISA and aspects of the x86 ISA. If you still think instruction sets can't be patented, just try challenging Intel about it in court. There will be a smouldering crater left where you once stood once the lawsuits are over with.

>High performance microarchitecture costs hundreds of millions of dollars to develop. Someone may develop competitive RISC-V CPU someday but it will not have open microarchitecture. AMD and Nvidia are examples of fabless companies who develop and sell proprietary microarchitectures. Thinking that someone develops open platform that competes with them is not realistic.

I am sure that they same argument should have worked for OSes 30 years ago. I think it will go the same way as it was with linux but much faster. There're a lot of small and not so small players who aren't able to develop microarchitecture themselves but quite eager to take their part in open source project.

I'm not sure that works as well for hardware. Every fab is different. Imagine if you had to rewrite the whole Linux kernel for every CPU on the market.

Getting high performance requires tuning carefully to the exact fab, and fabs change and upgrade on like a two year cycle.

To the best of my knowledge there's no equivalent to the C language for fabs. You have to port the whole chip every time

The same argument can be applied to the hardware. We have a lot of different hardware, it's all different, and every pice of hardware needs its own driver. In practice, drivers are created by hardware vendors and often they are open source.

Of course, production processes are more complicated than this, but there's a degree of decoupling of the processor together with its architecture from the production process.

AFACT, the only non-incremental innovations in CPU architecture these days is open source commoditization (the RISC-V approach) and taking VLIW to the extreme (the Mill Computing approach). Maybe we've hit diminishing returns, but both of those ideas still seem super promising to me.

The baffling thing is that we've got VC money coming out of our ears. They're funding unicorns with no hope of returns and funding every single uber-for-x idea under the sun. And yet it seems like both of these approaches have received almost zero funding in comparison. How is it that Mill Computing and SiFive (or any other RISC-V commercialization company), have not received billions of dolllars in venture capital yet?

What's the value proposition though?

SiFive is Berkeley is funding.

VCs invest in monopolies, not commoditization.

Customers buy into commodities when they are competitive with the monopolies.

VCs invest in ventures, and if those ventures are making money I don't think the they care what kind of market you're competing in.

I don't know much about SiFive, but I have heard that Mill Computing is bootstrapped and doesn't want to take any VC funding.

> AFACT, the only non-incremental innovations in CPU architecture these days is open source commoditization (the RISC-V approach) and taking VLIW to the extreme (the Mill Computing approach).

I'm still fascinated by the approach of Green Arrays; 144 tiny (forth) cores that together can lift about as much as a "small" cpu, but can also idle at low power with only a few cores active...

But That might be "too new"?

http://www.greenarraychips.com/

I also like the idea, but isn't it already tried with the transputer computer?

https://en.wikipedia.org/wiki/Transputer

And since programming is still mostly just chaining actions together, maybe we are just not very good at using other paradigms.

It's the same to an extent, but we're now in a world where chips are clocked 100x higher and we've squeezed dry the paradigm of making a serial core with faster and faster transistors.

An important difference from the Transputer is that it is an entirely asynchronous design that doesn't rely on a clock. It doesn't waste power idling just to distribute and keep a clock vibrating, unless you program it to do so.

The Mill is certainly novel, but I don't quite follow how "open-source commoditization" is non-incrementally innovative. What are the innovations with respect to other RISC architectures like MIPS or ARM? Or do you just mean the development model is likely to lead to more innovation?

The EE-times article is better IMHO. They hint at some SiFive customers. There's also a quote about embedded risc-v taking off already - if so I think we should see these appearing next year.

https://www.eetimes.com/document.asp?doc_id=1332398

> U54-MC Coreplex IP is the world’s first RISC-V based 64-bit quad-core application processor, supporting full-featured operating systems such as Linux.

Isn't the (still in draft state) Privileged ISA needed to implement a UNIX-like OS such as Linux?

The current version (v1.10) should be forward-compatible, and I believe is expected to be fully ratified in the next two months. There has been very little churn on it for a while now.

[Edit: RISC-V Linux is being upstreamed, and rocket-chip has been running Linux for years.]

Looks awesome. Seems like this hardware may be the start of a pivot back towards RISC for general computing.

Anybody have an idea if work has started on build of OpenBSD or FreeBSD for Risc-v? Would make an excellent chip for building super secure network edge devices or FreeNAS box.

Seems like this hardware may be the start of a pivot back towards RISC for general computing.

I doubt it. RISC-V will probably be seen more as "truly free and open MIPS", and maybe eventually start growing CISC-ish extensions --- they will have to if they want to become/remain competitive with other more popular architectures. Even ARM has become more CISC-y with the introduction of more special-purpose instructions.

Would make an excellent chip for building super secure network edge devices or FreeNAS box.

That is where I think RISC-V will find a lot of adoption --- since many low-end routers and other network devices already use MIPS (and have barely adequate performance.)

I don't think there's really any reason to think it won't take off in the datacenter, on Chromebooks, on Android devices, and network/embedded equipment as you mention.

Each of these will have a different timeline, but these days there are major markets which are more agnostic to ISA than they were five years ago.

The inherent commodity nature of designs and silicon based on a royalty-free ISA will drive down prices to the limits of design and material process, which will drive adoption.

If the processor adds more functionality, it should get more instruction, that's why it is extendable. However there is no reason to add specialized instructions for things that can be expressed at a lower level, and that would be CISC.

The data and test already done by clearly show that the core premise of the advantages of risc is true. The chips are less complex because of the feature set and use less area and less power.

Risc-V has been supported in FreeBSD since 11.0.

The FreeBSD RISC-V port has been upstream since FreeBSD 11, the Linux port will be upstream in either this or the next merge window. I don't know of anyone starting on an OpenBSD port, but that being good may be held up by the quality of the LLVM port. If they build it on upstream GCC, though, it should go fine I guess.

Very interesting, any information about a target price range?

Doesn't look like it but I would sign up on the bottom to get more info. (aside it should be on the top of the page)

This is an IP core rather than an actual SoC so the pricing will obviously depend on what else gets packaged with it, but based on the core+caches area of 0.538mm^2 on 28nm it should be competitive with the Cortex A7/A53/A35. As seen in Allwinner A64, Raspberry Pi, etc. It does say 2MB of L2 cache whereas most quad A53 SoCs I've seen have 512KB so the cost is probably going to be a bit higher from that. But full SoCs are likely going to be in the $5-$10 range.

The raw cost of the coreplex's silicon is probably ~7 cents. of course there's extra stuff that goes into a soc, but why do you assume it will go from 7 cents to $5-$10 ? is it because the cost of the A53 etc is insignificant ?

You have to take into account the end product, not just raw silicon cost.

There are costs in SoC packaging, wire bonding, testing, yield loss, warehousing, distribution, R&D, and profit.

Since when have the silicon costs been the slightest bit relevant to IC pricing? It's all about volume and recouping R&D costs and other NRE.

Yeah, but this core is open source, which significantly reduces the NRE costs for most integrators.

It looks like (although not 100% clear) it's available as hard IP, which means they've done the layout, but the very expensive mask NRE remains.

(They have a plan for an actual SOC but aren't shipping yet: https://www.sifive.com/documentation/freedom-soc/freedom-u50... )

The RISC-V ISA is free (i.e. you can design your own core without paying royalties to a company like ARM, which is what SiFive has done here) but this is a normal paid-for IP core. They do have some SoCs with a "free and open platform specification" but there's no public repo to download their Verilog code from.

If you want an actual open source RISC-V core, see: https://github.com/lowRISC/lowrisc-chip

The source here isn't their core?

https://github.com/sifive/freedom

That code seems to be for an FPGA devkit for their SoC but using an entirely different CPU core, the Berkeley Rocket Chip.

They're selling coreplex licenses for several hundred thousand dollars (not the one in the linked product page, it isn't for sale yet): https://dev.sifive.com/coreplex-risc-v-ip/buy/rtl/e51_corepl...

SiFive is a bunch of Berkeley people. Are you totally sure that their cores aren't rebranded Rocket cores?

> using an entirely different CPU core, the Berkeley Rocket Chip

Nope, the U54 and E31 are both Rocket, just with different parameters/configurations.

SiFive has continued to improve Rocket and contribute their improvements back to the available source code.

Hi, I'm one of the co-founders of the lowRISC project. You're right that SiFive's licensing arrangements can be somewhat confusing. Although they sell licenses (like https://static.dev.sifive.com/business/sifive-license-and-su...) which look like a typical proprietary IP agreement, the SiFive Coreplex IP is a derivative of the open-source Rocket chip generator. SiFive was founded by a team from Berkeley who produced Rocket, and are almost certainly now the biggest contributor to ongoing Rocket development.

Thanks for the clarification, it's not at all obvious from the website. The actual target audience buying $600k core licences is probably aware of all of this anyway.

Off topic question: has there been any work yet on a TileLink IOMMU? I was playing around with writing one, but didn't want to put in the effort if you guys or SiFive were just around the corner from releasing your own.

It's not something we've worked on so far at lowRISC. If SiFive have been working on something in that area I haven't seen them talk about it publicly.

Sounds like a great project, if you do start working on it I'd love to discuss more.

>> the SiFive Coreplex IP is a derivative of the open-source Rocket chip generator.

Any idea why they didn't drop in the BOOM core then? The EE Times article puts it at 30mm^2 with the L2 cache, so even a larger BOOM core wouldn't increase the die size much. Or are they aiming for really low power first? I could see a whole family of these coming over time. I hope this all goes really well.

While they could easily drop in a BOOM core, there would be some very non-trivial costs for SiFive to verify the IP and tune up the performance and feature set to match their costumers' needs. A lot of work has been put into Rocket once it made the transition from academic to professional and they would have to do that again for BOOM.

Also, there was quite recently a BOOMv2 paper describing some improvements, and hints of low-hanging fruits for further work. So I wouldn't be surprised if we'd have at least BOOMv3 before anybody commits to taping it out on ASIC.

The BOOMv2 authors apparently had taped it out in TSMC 28 nm HPM.

You just wrote that in response to a comment by one of the BOOM and BOOMv2 creators. And yes, there was more than just hints at low hanging fruit, so I'm hoping a v3 is in the works. But all those guys seem to be incredibly busy just giving birth to this (risc-v) thing.

BTW, just to put it in writing I'm estimating the BOOMv2 clock at 2.5GHz on 28nm. Depending how much IPC they clawed back it might match the A15 on coremark.

> You just wrote that in response to a comment by one of the BOOM and BOOMv2 creators.

Oh. Oops.. :)

This discussion brings to mind something Gordon Moore explained[1] about the economics of chip fabrication. According to this Intel co-founder it's all about selling silicon real-estate:

    What we end up doing is really selling real estate. We've sold area on
    the silicon wafer for about a billion dollars an acre, that order of
    magnitude, as long as I've been in the industry. Individual transistors
    used to sell for a few billion dollars an acre. The microprocessors
    today, too.  Maybe DRAMs are something under a billion.

So the cost of fabricating a wafer full of devices doesn't change much over time, but shrinking features means you get more devices for that cost. Notice the difference he points out between microprocessors and DRAM: all the costs involved with highly complex devices like CPUs ultimately still fall within the same order of magnitude as the cost of simple DRAM devices. The cost is some small number of "billions per acre" whether you're making the latest cutting edge circuit or just more arrays of bits.

[1] https://www.intel.com/pressroom/archive/speeches/gem93097.ht...

That's because there was some sweet spot under that figure. Bigger, lower tech transistors lead to a more expensive chip because it was too big, and smaller higher tech transistors lead to bigger costs because few companies could make them.

Unfortunately, that is all history. Current top of line fabrication processes cost more per area than their ancestors.

If that's the case, why there's such strong r&d effort on die minimization ?

To increase number of transistors without compromising speed and reduce energy consumption.

Nobody voluntarily transfers cost decreases to customers unless they have to.

I suppose the money for the wages of all the people working at the billion dollar silicon chip fab plant has to come from somewhere.

Because it will cost you 10 million dollars+ to produce your first chip. Every chip after that costs you 7 cents.

1.7 DMIPS/MHz seems to put it in the range of Cortex A5, maybe Cortex A7. But it also targets significantly higher clock speeds of 1.5GHz, so it may be faster than Cortex A7 in the real world. Probably not faster than A53/A35, but it should be close enough. Plus it has some additional features.

https://www.cnx-software.com/2015/04/09/relative-performance...

What may hurt it more in the market is the name. Most companies seem to underestimate its importance. U54-MC Coreplex doesn't exactly roll off the tongue...That means it's that much easier to ignore and forget about it. Hopefully whatever SoC will use it will have a better name.

Well the esp8266 80386, x86-64 or 741 chips didn't perform too bad either. ( I know x86 64 was an arch and not a chip)

u54 rolls off the tongue. Sounds like a u-boot, too. With a night club.

To compare with x86, 1.7 DMIPS/MHz is slightly less than the original Pentium (P5) at 1.88 DMIPS/MHz, and well behind the Pentium Pro (P6) at 2.7 DMIPS/MHz. Later x86 microarchitectures are vastly more efficient, with modern i7s achieving closer to 10 DMIPs/MHz.

https://en.wikipedia.org/wiki/Million_instructions_per_secon...

Isn't this pretty good then? P5-level performance/MHz from a pretty simple in-order scalar processor. And it clocks at 1.5GHz whereas the P5 topped out at around 200MHz. Though I suppose if you'd manufacture a (slightly tweaked) P5 on a modern process you'd reach similar clock speeds too...

Did I miss the privileged ISA specification passing?

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