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Comment by cjbillington | Hacker News Reader

Looking forward to CPUs getting on-die FPGAs so we can actually chuck some fully deterministic timing tasks onto them. Even if you're running on metal without an OS, there are heaps of things that can stop your code from running with predictable timing, and it seems like it's getting worse as CPUs are getting more complex.

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Related: reducing system jitter [1]

[1] http://epickrram.blogspot.co.uk/2015/09/reducing-system-jitt...

simple and super valuable article.

The PRU in some TI chips like that in the Beaglebone give you that kind of thing. A couple of deterministic 200mhz arm cores that run separately from the main cpu. They've been used for lots of motor control projects and also bit-banging network protocols.

Correction: they're not ARM, but a different RISC architecture.

We've had FPGA with CPU for 5 years or so on Xilinx Zynq. :)

Xilinx has being doing CPU+FPGA for longer than that. I did some C runtime enhancements for the PPC 440 included in the FX70 for a product made by a former employer (shadow stacks for better CFI, more locked down MMU use, etc).

Amusingly, Xilinx makes dev tools that are so unbelievably bad that it's almost impossible to do any of the best practices for development that you would hope for in safety critical systems. No source control, code review, reproducible builds, integration testing, centralized code review, etc.

Presumably you can sort of brute force it if you have defense level budgets, but it's a seriously bad situation.

Yeah last time I used Vivado a couple years ago, version control on the project was a nightmare. Reproducible builds seem to be a problem with stock FPGA synthesis tools in general.

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