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Comment by gok | Hacker News Reader

So is anyone designing RISC-V cores without using Chisel? :)

Yes, I am about 2/3rds of the way through designing and building a single cycle, modified Harvard architecture, RV32E CPU. You can check it out here...

https://hackaday.io/project/18491-worlds-first-32-bit-homebr...

Although a projected speed of 1Mhz and the size might exclude it from your own project!

I meant more like... just using straight Verilog, but very impressive!

I'm not sure I would recommend using straight verilog for something of that magnitude. I do know that some folks that used Perl to assemble verilog into a computer chip, but they regretted the engineering debt that came with it (and the hire they made that instituted that decision).

> Perl to assemble verilog into a computer chip

This is absurdly common.

Yeah there are a few out there. At Vectorblox we have ORCA that we use as a cross-platform replacement for nios/microbaze.

I don't know of anyone who has built anything as sophisticated as BOOM though.

Nvidia said they're not using Chisel for the RISC-V cores they plan to embed in their GPUs.

see https://www.youtube.com/watch?v=g6Z_5l69keI&t=545

There is PicoRV32 [1].

[1] https://github.com/cliffordwolf/picorv32

Yep and there's https://github.com/SpinalHDL/VexRiscv

But admittedly, SpinalHDL is basically Chisel.

There is the PULP project (http://www.pulp-platform.org/) by ETH Zurich and University of Bologna with different open-source RISCV cores written in (System) Verilog.

Yes, see Syntacore's SCR1, Clifford Wolf's PicoRV32,etc.

Granted these are smaller, microcontroller-class cores, but still in pure Verilog. I'm sure there are others out there with more/less performance

Here's a collection of RISC-V cores in Bluespec: https://github.com/csail-csg/riscy

plenty. not as many open source ones though.

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