Hacker News Reader

Comment by monkmartinez | Hacker News Reader

Is anyone else just completely lost inside Intel's Canyons and Lakes? To carry the analogy a bit further, the maps I've found that detail the Lakes and Canyons aren't much help due to the Core, Pentium and Celeron monikers.

At this point, does it matter much? I have a Celeron Qnap 25X that chews up everything I throw at it, the only limitation is the 8GB of RAM. IN fact, the limitation doesn't seem to be the processor on any of my stuff. It is either a dearth of supported RAM (like 8GB max), or a lack of an SSD or slow SSD's (which is another confusing topic eVVM, NVM, etc...).

View on HN

> At this point, does it matter much? I have a Celeron Qnap 25X that chews up everything I throw at it, the only limitation is the 8GB of RAM.

It surely chews no code containing AVX/AVX instructions. Also support vor VT-d is probably missing, just as TSX. Not to speak of AVX-512, which is planned by Intel to come to prosumer processors in near future.

I have Container station[1] and Virtualization Station[2] running fine...

[1] https://www.qnap.com/solution/container_station/en/ [2] https://www.qnap.com/solution/virtualization-station/en-au/

How much does that matter?

I get most of my software pre-compiled through apt repositories. It's all using basic X86_64 instruction sets. My computer, being a relatively recent Core i5, has plenty of advanced features [0], but outside of one piece of manually compiled software occupying less than 5% of my CPU on average (an LP solver used by a bot), I'm not taking advantage of any of it.

Considering how much electron apps have taken over my desktop, SSD and RAM play an exponentially bigger role in the quality of experience than my processor does.

[0] https://ark.intel.com/products/91160/Intel-Core-i5-6260U-Pro...

Java, V8, or the .net CLR could sense the processor features at run time , and JIT the code into more efficient instructions?

A lot of things are interpreted nowadays, if the interpreter is updated to understand the processor features, it can take advantage of it.

In addition to JIT-compiled code there also are libraries that do runtime detection of available processor features and dispatch to optimized implementations. Pretty much anything number-crunchy such as software image/video processing will do this.

How much do these VMs actually optimize with newer instructions? Last I checked (oracle java 8), the jvm still had really spotty autovectorization optimizations, and SSE has been around since 1999, with the most recent SSE4 coming out over 10 years ago. I get that they technically could do so, but how much do they do it in practice?

I don't know of anything using TSX, AMD doesn't have an equivalent in Ryzen even, I wouldn't bet on Zen 2 having it either. If you have a new enough Intel CPU, OpenCL on an Iris GPU is better than or as good as AVX/2/3 by far.

VT-d not being in every processor is Intel's fault for using binning to gouge consumers. Though everyone doesn't need VMs or containers.

VT-d is a prerequisite for TXT, which has value to people who aren't using VMs or containers.

VT-d also enables device driver containment/isolation, again, which provides value to people not otherwise interested in VMs or containers.

I'm not sure I would phrase it that way, the two are relatively independent. If you're getting a business laptop, you're likely to get VT-d and TXT. The i7-4710HQ has VT-d and doesn't have TXT or vPro.

https://ark.intel.com/products/78930/Intel-Core-i7-4710HQ-Pr...

TXT is more a part of vPro and provides bootup security, including drivers loaded at startup. Everyone doesn't need VT-d or TXT. Most BIOSes support some sort of signing if you bother to setup it up and verify that your kernel hasn't changed. Intel could have made vPro, TPMs and TXT open and available to everyone, regardless of VT-d, but that's how they chose to differentiate and make a little more money. Mom and pop need to settle for basic kernel signing instead of an open TPM module.

Reply on news.ycombinator.com