Graphs not Grids: How caches are corrupting algorithm designers (2010)
blog.ezyang.com
blog.ezyang.com
Here's an approach for the massively multi-threaded CPUs that may be complimentary: versioning the memory so you can speculatively execute tasks: http://people.csail.mit.edu/sanchez/papers/2017.fractal.isca...
Putting it together sounds like a dream.
Sounds like a less granular version of hyper threading.
> versioning the memory so you can speculatively execute tasks
The more you speculatively execute the less you actually execute. With more threads you don't have to try to squeeze more granular parallelism at the cost of diminishing returns.
True, but there are lots of graph-type problems where it is very useful. As explained in the paper I linked to?
Are you asking me if the paper you linked to explains it?
You are saying "it's useful", I'm saying it quickly becomes too wasteful. CPUs already do speculative execution with the hopes of mitigating memory latency.
I'm saying if you spend all your transistors and power doing speculative execution, it is better to find an architecture that lets you use concurrency on a much courser level so that you don't have to waste so much doing speculative execution, only to get diminishing returns for the transistors and power you put in to it.
There are lots of hardware that has embarrassingly many cores which are underutilized on embarrassingly serial graph problems. Speculation is one way to get all those cores humming if you have a good heuristic for what is likely to be true and the hardware has versioned memory and hardware scheduling so as to make the speculation cheap enough.
The paper gave examples of such problems.
Coarse-grained SMT (what Intel call 'hyperthreading') is when a core swaps to a second task when one task stalls on a main memory access.
Intel chips typically have just two tasks they can pingpong between.
The Cray XMT takes this much further with a very long list of tasks it can swap between, with hardware caching, ready-monitoring and scheduling of them. This is excellent for graph problems with lots of main memory stalls. There are plenty of graph problems where there are many tasks that can make progress but they are all waiting on main memory all the time.
The research I linked to takes it further and allows the tasks to be executed speculatively. Basically a tree of hardware transactional memory.
Everything you say about speculation being cycles you can't use for non-speculable computation is true. But there are problems with bottlenecks that force them to be essentially serial.
When cores are cheap, the problem doesn't fit in on-chip-cache and the buffers needed for SMT or SMT+speculation are affordable, speculation is a good way to utilize cores that would otherwise sit idle if that fits your power budget.
Also OOO cores already pre-load things into memory so they can be actually executed, not speculativly executed. Speculative execution on modern CPUs will execute both sides of a branch to prefetch data further.
What I'm saying is, if you traverse a graph with tiny amounts of data at each node, it is wildly inefficient. Mitigating that inefficiency with more hardware might be faster, but is still an inefficient use of hardware since it doesn't confront the real problem of skipping around in memory.
The only way any of this makes sense is if the article is talking specifically about graph processors (e.g. the Cray Eldorado, which to be fair, is mentioned), but there are very few commercial graph processors and even those are shrinking in importance. The number one parallel processor is the gpu, the only one with any chance of making it into the mainstream, and even that is far from mainstream. And the gpu hates control flow and sparsity.
i'm extrapolating from the talk, but i think the point is that architectures that can tolerate dynamic flow control (mimd) are more performance general than ones that cant. and while no, they aren't mainstream, I think the historical jury is still out.
since the cost of keeping an instruction pointer per unit is (largely) absorbed by hardware, its pretty easy to argue that they should win in the limit. unfortunately there are other costs, the memory interface is vastly different. caching becomes interesting and potentially prohibitive.
but is mimd dead forever because gpus can be used for some things and are clearly the cheapest ops you can buy today?
Because the programming principles espoused in this article are antithetical to what you should do on a GPU, which is definitely the de facto "massively parallel processor" that would first come to people's mind.
it is worth noting that the El Dorado started out as a general purpose computer, then a general purpose scientific computer, and then later as a "graph processor" in an XT frame because the MTA on its own was market-dead. and that Feo has been a big supporter since at least stage 2.
maybe is exactly this 'parallelism means GPU' which he's trying to argue against. I agree the overall arch of that point didn't really follow through in his talk, or someone's summary of that talk.
'mpp' was certainly a label adopted by TMC's cms 1-2, which were pretty damn simd. its was also used by the cray T3e, which was markedly not. the mta had 128 threads per cpu. a large enough instantiation could have had a few thousand hardware threads. later unbuilt designs backed the thread state in dram and could have gotten pretty damn fat. arguably 'massive' should be squishily about concurrency width.
graphs -> linear algebra