Other than x86, do many processors permit either of those things--1) unaligned atomic operations, or 2) type-punning where memory ordering is guaranteed for a 32-bit read of a 64-bit atomic write.
But two 32-bit words can span a cache line if the first isn't 64-bit aligned. So what you're doing relies on hardware supporting atomic operations not only on unaligned words, but on words spanning cache lines. Are you really sure ARM and POWER support that?
On x86 a 64 bit atomic can span cache lines.
> Are you really sure ARM and POWER support that?
Do they not?
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
On older processors, such as ARM9 family based processors, an unaligned load had to be synthesised in software. Typically by doing a series of small accesses, and combining the results.
"The ARMv6 architecture introduced the first hardware support for unaligned accesses. ARM11 and Cortex-A/R processors can deal with unaligned accesses in hardware, removing the need for software routines."
Apart from Load-Exclusive, Store-Exclusive, Load-Acquire,
and Store-Release, addresses can have any alignment unless
strict alignment checking is enabled....
-- Section C3.2 Loads and Stores, page C3-160.
The Load-Exclusive/Store-Exclusive instructions other than
Load-Exclusive pair and Store-Exclusive pair require natural
alignment, and an unaligned address generates an Alignment
fault. Memory accesses generated by Load-Exclusive pair or
Store-Exclusive pair instructions must be aligned to the
size of the pair, otherwise the access generates an
Alignment fault.
-- Section C3.2.6 Load-Exclusive/Store-Exclusive
The Load-Acquire/Store-Release instructions other than Load
Acquire pair and Store-Release pair require natural
alignment, and an unaligned address generates an Alignment
fault. Memory accesses generated by Load-Acquire pair or
Store-Release pair instructions must be aligned to the size
of the pair, otherwise the access generates an Alignment
fault.
-- Section C3.2.7 Load-Acquire/Store-Release
The LoadLOAcquire/StoreLORelease instructions require
natural alignment, and an unaligned address generates an
Alignment fault.
-- Source C3.2.8 LoadLOAcquire/StoreLORelease
The CAS and CASP instructions require natural alignment, and
an unaligned address generates an Alignment fault.
-- Section 3.2.12 Compare and Swap, page C3-172
The LD<OP> and ST<OP> instructions require natural
alignment, and an unaligned address generates an Alignment
fault.
-- Section C3.2.13 Atomic memory operations, page C3-173.
The SWP instructions require natural alignment, and an
unaligned address generates an Alignment fault.
-- Section C3.2.14 Swap, page C3-175