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Comment by slizard | Hacker News Reader

This looks like a solid if not amazing comeback of AMD into the server market. Sure, single threaded performance may not beat Skylake-SP, nor will the LINPACK (and most wide SIMD/FMA-heavy works) performance, but that still leaves most of the HPC/engineering applications that either do not have workload that lends itself to heavy vectorization or are simply not tuned for it (and won't be overnight).

All in all, whhen you have a server that seems so close in performance to Intel for less money and consuming less power, I can't imagine that EPYC won't see broad adoption and Intel won't be squeezed.

I'm glad AMD is back and there is renewed competition in the server market!

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Not to mention AMD has a very clear Roadmap for Zen IPC as well as node. Compared to Intel which has been delay after delay or rename. There will be Zen+ next year on 7nm, and 7nm+ in 2019. Not sure if they are the same on Server, but they are suppose to fit in the same socket on Desktop.

Good point, it looks like they have a decent path forward and hopefully they take good advantage of the new nodes and the available room for refining the uarch.

Socket compatibility would be wise, I hope at least the Zen+

I'm hoping they soon get back to competing aggressively at high-end HPC too, perhaps they could spend some area on Zen+ on better FP SIMD, or even flexible width SIMD (though the latter would be more realistic on the 7nm successor).

I wonder if even the AVX512/other SIMD boost is even worth it when you factor in pricing.

It will take some time until that question can be answered. For some it will likely matter a lot, e.g. engineering or HPC applications that rely heavily on dense solvers. however, even for non FP-heavy workloads (like integer-heavy stuff say databases) the wider SIMD with the new mask and blend instructions [1] _could_ make a significant difference. Still, in many cases significant difference will likely be seen only after careful tuning!

Also note that Intel is refining their pesky market segmentation game: the full 2x 512-bit FMA/cycle is only available on high-end CPUs, only lower-end it's only 1 FMA/cycle and you still get the extra AVX512 clock throttle hit [2]!

I really like the fact that AMD stayed away from such devil-in-the-details feature-based market segmentation!

[1] https://software.intel.com/en-us/blogs/2013/avx-512-instruct... [2] https://www.servethehome.com/wp-content/uploads/2017/07/Inte...

Wide availability of an ISA creates the economic opportunity for people to hand tune / optimize for it. I wonder if Intel is shooting themselves in the foot by creating instructions that are available only in a tiny fraction of shipping CPUs. AMD would have had a much harder time with Ryzen if AVX 512 was shipping in volume on a bulk of the chips and if a wide variety of software had been written to exploit it.

Depends on the size. Sure AVX512 is great until either A) you thermally throttle or B) you cache miss. Keep in mind that AMD has 8 memory channels vs Intel's 6. So if you need to hit main memory (randomly or sequentially), AMD has a decent edge.

Agreed, see my point below (/item?id=14747906).

HPC and scientific computing are quite small niches of the server market though. The database, java etc benchmarks are more important in making or breaking it as a commerical product.

Sure, but I was addressing the areas where the Zen arch is clearly not beating Intel. Database, java, etc. are areas where the initial benchmarks indicate that EPYC is quite competitive.

In this article, EPYC did ok on Java but very poorly (~half speed vs Intel) on MySQL.

But the article states that they didn't have enough time to tune (they had the chip for just a week compared to 2 weeks for Intel) and a more detailed look is forthcoming from Anandtech, so it might be wise to wait for that.

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