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jnordwick

I didn't see any info on the cpu cache architecture which governs performance for many applications now.

Anybody have any info on things like L0 to L2 size, type, latencies, etc?

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Our original Zen Microarchitecture deep dive has all the info.

http://www.anandtech.com/show/11170/the-amd-zen-and-ryzen-7-...

This gives a really bad picture of AMDs cache performance. The all important L1 and L3 are much slower than Intel. No bueno.

https://www.techpowerup.com/img/17-03-06/7ca3a1705392.jpg

You have to be careful when comparing latencies as the numbers can be completely meaningless depending on workload.

Also, note that the numbers have changed significantly for Zen since its original launch due to updates from AMD/Manufacturers, so many of the numbers you see in older reviews are no longer accurate.

If you read reviews of the new Intel processor today, you'll see latency numbers have increased for Intel with their new architecture:

https://www.pcper.com/reviews/Processors/Intel-Core-i9-7900X...

In the end, workload-based performance metrics tend to be far more meaningful than synthetic benchmarks or simplistic latency measurements.

They mentioned in the article that the full cache of each die is available. Additionally, EPYC uses the same dies used in Ryzen. I'd look at earlier articles for Ryzen to determine latencies within a single die.

So for whatever cores are enabled on each die, you get the L1/L2 caches for each core as per the Ryzen launch. Additionally, you get all of the shared L3 cache, irrespective of the number of cores disabled per core complex. This pattern follows across all four dies in each socket.

I read that, but how much, type, architecture, latencies, etc? This is a huge factor in the performance of the chip.

"Each Epyc has 64KB and 32KB of L1 instruction and data cache, respectively, versus 32KB for both in the Broadwell family, and 512KB of L2 cache versus 256KB. AMD says Epyc matches the Broadwells in L2 and L2 TLB latencies, and has roughly half the L3 latency of Intel's counterparts."

https://www.theregister.co.uk/2017/06/20/amd_epyc_launch/

Various L3 sizes in the article.

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