Besides reasons already mentioned above (and adding my own emphasis on suboptimal power performance), CPUs have GHz-scale clock domains, thanks to pipeline stages that minimize the number of gates traversed on each cycle. FPGA designs often run at frequencies ~10x slower. While one could instantiate pipeline stages using FPGA's logic calls, it's badly inefficient use of silicon. Maintaining separate clock domains, on the other hand, also consumes lots of silicon due to needing to isolate the domains, to avoid injecting noise into shared power/ground planes.