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Someone needs a tool chain with chisel as the target.

Why not target verilog directly? Chisel is just a verilog generator in the end.

Because of ML and neural networks hype. No one wants to learn VDHL or Verilog, they want OpenCL or something similar.

I hear what you're saying, but Chisel is a lot closer to an RTL like Verilog than it is to OpenCL.