IBM’s world-first 5nm chip indicates EUV lithography is ready for primetime
arstechnica.co.uk
arstechnica.co.uk
This is the real message, because creating 5nm chips was already possible[1]. However, creating them massively on scale with the ASML EUV machines is the real challenge.
[1] https://www.semiwiki.com/forum/content/5080-imec-cadence-dis...
They need large volumes of cost effective processors as well. Manufacturing their own special purpose asics with older technology is more likely.
EUV has been available for years and no doubt TSMC and SS have their own EUV test chips at 7nm (comparable to Intel 10nm), but the EUV equipment business will be validated by large orders and $ spent, not on prototype silicon. We aren't there yet (but probably will be in a year or so- they've gone from 100W to 150W in the last 9months and need to hit 200-250W).
Will we have 1-3nm transistors? Yes. Will they be commercially viable? Probably No.
Moore's law ends when the CFOs decide it's not worth building another multi-$B factory on schedule based on net expected return... which already happened over the last 4 years. Sorry, downvote at will.
Why not? We can only stack our layers so much, eventually the 1-3nm range of transistors will become useful to give technology another squeeze before having to learn how to layer a bizarre number of layers.
The pure military stuff tends to be in the sensor space. DARPA has some projects to build much better accelerometers and gyros on ICs. They want cheap inertial navigation to back up GPS.
It's possible to reach much higher densities by writing an IC with an electron beam. This is slow, but useful for one-off jobs. DoD is known to be using that.[1] "DoD foundries make a wide variety of custom chips in small quantities - the exact opposite of commercial practice." Interestingly, the USAF is doing this partly because they don't trust off-the-shelf chips not to have "backdoors".
IBM split off and kept the R&D part of the foundries and sold the manufacturing aspect to GlobalFoundries.
[1]http://www.acq.osd.mil/se/briefs/2016-TrustPolicy-Baldwin.pd...
Then there's the matter of using this for production of large scale shipping chips. Note the POWER9 (IBM's next big chip) is expected to be produced on 14nm.
> we'd need a paradigm shift?
Yes we're coming to the end of the road for traditional CMOS chips. I don't think anyone really knows what's next as there's no clear successor.
I would speculate in the coming years we'll be seeing more performance coming from invocations in the data path for general purpose computing. Of course exploitation of massive parallelism will continue.
I would assume that maximum yield would be achieved by very accurate machinery making coarse chips, like using 14nm lithography to make 22nm chips, but this is rarely done in practice, I think.
"The company’s 0.13-µm chips, which debuted in 2001, had transistor gates that were actually just 70 nm long. [...] Through all this, node name numbers continued to drift ever downward, and the density of transistors continued to double from generation to generation. But the names no longer match the size of any specific chip dimension. “The minimum dimensions are getting smaller,” Bohr says. “But I’m the first to admit that I can’t point to the one dimension that’s 32 nm or 22 nm or 14 nm. Some dimensions are smaller than the stated node name, and others are larger.”
The switch to FinFETs has made the situation even more complex. Bohr points out, for example, that Intel’s 22-nm chips, the current state of the art, have FinFET transistors with gates that are 35 nm long but fins that are just 8 nm wide."
If there wasn't such an enormous difference between the two, I bet some foundries would have silently started reporting transistor sizes in nautical miles (nm) in order to ensure the number kept decreasing.
Using light: http://gizmodo.com/a-new-light-based-transistor-could-comple...
Building on memristors: http://www.memristor.org/reference/research/13/what-are-memr...
http://spectrum.ieee.org/semiconductors/design/the-mysteriou...
Neural network inspiried chips: http://www.research.ibm.com/articles/brain-chip.shtml
I think we will see some breakthrough after the CPU industry goes into an existential crisis about going below 5nm. Current pipelines are just so damn expensive to replace that we will see gradual innovations. For example TPU-s[1] might be a standard in a few years like GPU-s are now.
The current trends are clearly in reducing power usage and size. That alone will be a huge innovation when I can hold a "server farm" in my pocket.
Light-based communication probably will replace certain I/O blocks on chip. These tend to be quite large in terms of area after considering power and ESD constraints.
[1] Discussion here: https://news.ycombinator.com/item?id=13051984
> but this is still far from the realm in which it makes sense to replace an electronic transistor with an optical transistor
The electromagnetic spectrum even at mid-near infrared wavelengths frequencies could help chips operate on the THz scale! You might list a mountain of reasons it can't work, but it's just fun to imagine that it might be possible to turn a cycle of light to an operation.
You can build interesting things at that scale, in this research they also refer to communication as you mentioned [1]
Thanks for that link, I downloaded the paper :)
[1] http://newscenter.lbl.gov/2011/05/31/nanoscale-waveguide-for...
What you should be asking is how many molecules of silicon and silicon-germanium can be packed into the spaces being talked about at the different fabrication levels of 14nm, 10nm, 7nm, 5nm, and so on.
Once you have that information then you can ask what is the smallest number of molecules that these processes can scale down to. Only then we can start asking about physical limits and more exotic processes. Are we talking about features of 50 or 40 molecules across or what?
All I know is that 1nm is not a magic number and that predictions about the demise of transistor scaling have always turned out to be wrong. My prediction is that, as unimaginable as it seems, we'll be able to scale down to the physical limits of the materials.
So that's like 1nm?
This is very important to be pointed out. The burden of proof should be on the people who suggest that "this time it is different", not on those who correctly assumed that technology tends to progress in time.
What are these physical limits of the materials?
Until we are building on a single atom, and even then maybe we can go smaller.
Can you elaborate?
There are people doing research on subatomic who think that various quarks have interesting properties for computing. This may or may not be possible. But we likely don't know yet.