> all 64 lanes being enabled for all ThreadRipper SKUs. This will be broken up into 60+4: 60 lanes directly from the CPU for feeding PCIe and M.2 slots, and then another 4 lanes going to the chipset
And
> the 16 core processor will for most purposes be half of an Epyc processor
Epyc (formerly Naples) is the server-grade arch with 8 memory channels, 32 cores and 128 PCIe lanes per socket.
Well shit... what am I going to do with this pair of useless Xeon E5s I just bought?
Or maybe there's one less chip in the package?
Half. Epyc gets 4 MCM[0], ThreadRipper gets 2 (with each MCM containing 8 Ryzen cores)
But I believe it only when I see it. Especially since the rumors said Threadripper will only have 44 PCIe lanes like Intel, which as we now know was false (and was weird previously because Naples has 128 PCIe lanes).
The issue with binding is the larger and more complex your die the more failures you have. But breaking it down to 2 smaller dies that are combined they reduce this since they are already getting relly good yields out of the ryzen7 dies.
Epic is just 4 ryzen7 dies. So no this is not worse bins the 16core threadripper is 2 ryzen7 cores.