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In general, code meant for sequential processors (even massively parallel sequential processors) doesn't really translate into the potential gains you see from FPGAs. I'm pretty skeptical that this gives you any gains.

Even OpenCL->HDL wasn't the huge boon it was supposed to be.

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1) You're right. The problem here is the unpredictability of the buffer's size - it's equivalent to halting problem in general. You miss just one item in the buffer and you risk circuit not working at random times.

2) OpenCL->HDL takes hours to complete due to need to synthesize, whereas OpenCL->CPU code takes seconds at worst. The time to get working (synthesized) code is major blocking factor in utilizing FPGAs anywhere.

Do you think pure paradigms could be mapped, or are you skeptical of any general purpose language being able to efficiently compile to FPGAs _and_ CPUs (and GPUs)?

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