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Comment by m-j-fox | Hacker News Reader

I wonder why it needs so many pins? It only has 4 DDR channels, which is going to be a bottleneck keeping those cores fed. 8 channels would be more appropriate for 16 cores and it would explain why so many pins.

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It needs a lot of pins because it's an I/O monster. The socket is going to support their high end server chips with 8 memory channels. Plus, all of their high end line supports 128 pcie lanes, and will have on board an unknown number of usb, sata, and networking lanes. All that adds up to needing a very large socket.

That article points out it's a different version of the core on the desktop, SP3r2 instead of the SP3 that is landing server side. SP3r2 is only coming with 4 DDR channels.

It's not clear why they're deliberately using a crippled socket here for the desktop. I don't understand the value proposition, and can only envision it driving up motherboard prices. That CPU combined with a crippled socket is surely likely to end up starved of memory IO

Sp3 is for 32-core chips wirh 8-channel memory. Sp3r2 is for 16-core chips with 4-channel memory. The reason the Sp3r2 platform exists is to make motherboards cheaper -- the lines for 8-channel memory force you to use more layers, increasing cost.

They are using the same large socket to reduce time to market -- they had validated the 8-channel socket, they don't currently have a modern 4-channel socket, and they think there is demand.

The Naples chips also have 4094 pins and do have 8 channels as well as support for 2+ CPUs per board. Maybe these Threadripper chips are Naples chips where memory controllers or interprocessor communication controllers failed QA?

> Maybe these Threadripper chips are Naples chips where memory controllers or interprocessor communication controllers failed QA?

I'd be highly surprised if they were anything else.

Ryzen = 1 piece of silicon, cheap, 4-8 cores, 2 mem channels Threadripper = 2 piece of silicon, midrange, 8-16 cores, 4 mem channels Naples = 4 pieces of silicon, high end, 16-32 cores, 8 mem channels.

I would assume that most of the pins are power/ground, like most high-pin-count sockets. They help avoid system noise at really high clock rates.

Intel are moving to a similarly big socket for next-gen Xeons, LGA-3647 [0]. It's already in use for socketed Phi processors.

[0] https://en.wikipedia.org/wiki/LGA_3647

It's probably the same socket as Naples (=four die MCM with 128 PCIe lanes and 8 DDR4 channels).

This would mean that this is a two die (active) MCM with a maximum of 64 PCIe lanes.

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