Show HN: R8 Processor
hasaranga.com
hasaranga.com
Are you planning to extend the ISA at all?
Looking at the source, though, this processor uses a variable length instruction; so it is at least a bit CISCy.
IMHO 'Real' CISCs potentially have multiple memory addresses "add m1, m2, m3" sort of things and addressing modes that do double indirections (remember a worst case VAX instruction could generate [I think] 27 different TLB misses which meant that the smallest process had to have an at least 27 page minimum working set to let every program progress - for a RISC machine it's just 2)
Really though what happened between RISC/CISC was largely driven by a change in the relative speeds of memory and CPUs - CISCs made sense when memory bandwidth was low and heavy encoding reduced instruction bandwidth, RISCs (or RISCish including x86s) have come to dominate as caches moved on-chip and bandwidth soared
Some other boards a pretty small. I have a Xilinx Spartan; really easy to carry around.
https://github.com/polysome/aggregate-1/blob/master/README.m...
[0] - http://dangerousprototypes.com/blog/2011/04/22/avnet-spartan...
https://getchip.com/ http://linux-sunxi.org/Allwinner_SoC_Family#.22R.22-Series
[1] https://www.arm.com/about/trademarks/arm-trademark-list/
[2] https://www.renesas.com/en-us/products/microcontrollers-micr...
are there any tutorials for this?
If I'm understanding you right don't have a former license yet. You could use something like MIT, Apache 2.0, CC0, GPL, LGPL or WTFPL, that would fit your comment.
I think MIT or Apache 2.0 would be the safest choices (if you don't have a preference for GNU/copyleft licenses).
I'm afraid a HN comment won't hold up in court as proof I have a license to use a work.
Please let me know if you made anything useful with this processor!