As a Haskell fan I was drawn toward VHDL because of its "strong typing". Haha, it's nothing like what I expected, mainly just a bunch of annoying forced casts from signed to unsigned etc. I ended up liking Verilog better: more characters are dedicated to your intent than to your casts. But ultimately they're not that different.

(Note there are also Haskell-oriented HDL's, but my experience with those wasn't great, at least 4-5 years ago. Proprietary, poor interop, and let's face it, it's not Haskell. On the surface FP seems like a good fit for FPGA, but in the trenches you constantly need lower-level tricks to keep your program's gate count from exploding.)