I last did either VHDL or Verilog in 1997, which is 20 years ago (and reminds me I'm getting old), but if things are remotely similar, the apt comparison is not ARM assembly vs. MIPS assembly, but rather Verilog=~C vs VHDL=~Ada
Example Ada: http://perso.telecom-paristech.fr/~pautet/Ada95/e_c16_p5.ada
This is actually a good thing, Verilog (and even more SystemVerilog) is designed by people who don't have a clue about language design resulting in an incredible mess of a language.