What can happen is to make chips simpler in that less computation is spent in instruction decoding, tracking, scheduling and more is spent on actual execution.
These problems seem to be what VLIW architectures like tried to to solve. Is that sort of architecture going to make a comeback? Will even that help?
16 registers is not a lot when compared to other architectures. POWER, SPARC, Arm64 and MIPS have 32 (SPARC is weird, but 32 are always visible). Itanium has 128.
Also you're probably aware that modern CPUs have many more physical registers, they just don't expose them all at the same time.
E.g. AMD Zen physically has 168 integer and 160 floating-point registers. Of which you can only use 16 at a time, but to my uninformed eye that looks like a reasonable trade-off.
If you want your CPU to run fast, you have to pipeline instructions and you need caches that can run at full CPU speed. It's easy to design a CPU without all the complexity, but it will be slow. No one knows how to do both simple and fast. It's probably impossible.
For machine learning applications, I don't think the end game is to have complex CPUs, though.
Assuming that brains have managed to find more than a local optimum and that our understanding of them is somewhat accurate, ditching all those caches, translation buffers, etc. most of the bus bandwidth, and moving computation towards memory is the way to (eventually; we need to learn a lot before that's feasible) go for machine learning applications.
Does the brain even have instruction decoders?
I can't even begin to understand this question. It makes no sense at all.
There is absolutely no reason to reach that conclusion.
If you look at a particular technology node, one of the best correlations of power consumption is chip area. It's pretty much a straight line.
Now, that has probably changed a bit with how aggressively we turn chip areas off nowadays. So, we probably have to alter that to power consumption vs active chip area--but it's still a fixed line for a technology node.
It'd be, of course, totally incompatible with what we have now.
Whose only competitor is ARM, which is little better in terms of decoding complexity.
T32 indeed has this problem, but not A32. With ARMv8 ARM released the A64 instruction set, which is designed new from ground up and is to my knowledge also not hard to decode. Nevertheless decoding complexity is not that relevant anymore. What is much harder and involves more die area is (super-)pipelining the execution, out-of-order execution etc. But even all this together: What consumes most die area are typically the caches.
The careful balance of every aspect of a modern CPU is an art very few people practice. I'd say IBM and Sun have't left this game just yet for very high performance platforms, but don't expect a Core i3 coming out of either.