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Comment by heathjohns | Hacker News Reader

I don't disagree. I'm reasonably optimistic that current and near-future FPGAs are overkill enough for the job of motherboard chipset and basic peripherals that that some basic portability abstractions can be put in place (e.g. ASM -> C) without causing such a performance hit that it's not viable any more.

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I think it will still be a very uphill battle to get such chips integrated anywhere for some very basic reasons: power and heat.

All those extra transistors that allow FPGAs to be reprogrammable also dissipate a lot of heat and use a lot of power (or did back when I was mounting massive heatsinks on custom networking FPGAs).

For a laptop or phone manufacturer if the choice is between an ASIC and an FPGA that consumes 10x the power it is an easy choice. It's not just dollar cost, but power and heating budgets.

In general I love the idea.

Things have been changing - they put FPGAs in phones now:

https://www.ifixit.com/Teardown/Samsung+Galaxy+S5+Teardown/2...

(search for "FPGA" in the page).

That's a tiny one, granted, but things are certainly getting better in that regard.

CPLDs have been pretty commonplace in complex embedded system designs for a while. They're great for consolidating a bunch of little logic bits into a single package, and allow you to build some control logic using code rather than iterating hardware when you need to make small changes. There's huge advantages for a system like a phone where you are extremely space-constrained, and also with quick turn engineering cycles where the hardware can't go through 6 revisions before being completed. Throw a CPLD or a low-power FPGA like the Lattice ICEstorm series in there and let the HDL do the rest!

I've also seen CPLDs used to recover from board layout mistakes.

That's cool to see, although given the exploding Samsung Galaxy phone situation (probably completely unrelated) I'm not sure their engineering of power consumption/cooling is the best thing to cite. :)

A defective battery is about as far as you can get from chip design.

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