There should be much better errors/warnings letting you know when you've written VHDL/Verilog that doesn't turn into standard logic gates and systems, when you've done things that have easy to identify race conditions, and when you've written things that just don't make sense.
After working with computer code compilers, and analyzers like lint and clang, it is still sad to look at the errors (and lack of errors) coming out of VHDL/Verilog tool chains and not see something even 2 orders of magnitude of useful as far as toolchain output. WAY too much Field application engineer time is spent on junior engineering problems that can't be effectively delegated due to this insufficient machine error checking.
I mean, half the time you generate something that will simulate differently than run in real life, that's OBVIOUS from the code structure. But no, the toolchain doesn't identify that, bench checking the specification to the VHDL is the only way to find that (or a code review by another engineer).
So TLDR: Make VHDL or Verilog spit out REAL errors and warnings when used somewhat incorrectly, or likely incorrectly. Bring the tools up to the standard of sequential coding tools, or even more in that direction instead of the morass it still is today for hardware specification languages.