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The article says that it has 8mb of cache per core, shared by four hardware threads.

The article is mistaken; the 8 MB is shared between the 50 cores. There's some speculation that it might be a Non-Uniform Cache Access architecture, where local parts of the shared cache are faster to read/write than other parts. If so, that would certainly be an impressive step. A better article is here:

http://www.channelregister.co.uk/2010/06/01/intel_knights_co...

That's 400MB of cache on the die, which seems highly unlikely.

That would be far more remarkable than putting 50 cores on the die. It would be cause for riotous celebration.

> riotous celebration

Well, maybe. There are diminishing returns on increasing cache sizes (you solve the capacity misses but don't really deal with compulsory and conflict misses)...though it would be impressive an impressive feat of process technology. The closest to that amount at the moment I believe is IBM's Power 7, which has a 30MB on-die L3 implemented in eDRAM.

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