X-rays could be used to cut down on problems bringing a new CPU to market | Hacker News Reader

X-rays could be used to cut down on problems bringing a new CPU to market

arstechnica.com

64 pointspoiuz21 comments

The article doesn't make this clear, but this is an excellent example of an area where "pure research" and practical technology overlap. Free electron lasers are essentially particle accelerators (of the same sort used in, e.g., the LHC) with special configurations of magnets stuck on the end. They are large, expensive to build, and expensive to operate for essentially all the same reasons that research accelerators are. So advances in physics which lead to advances in accelerator technology, which allow further advances in pure physics, also directly impact the practicality of using FEL X-ray sources for imaging microchips (among other things).

They aren't "essentially" particle accelerators, they are full-blown accelerators, linear accelerators, specifically.

Most of the problems with binging new digital ASICs to market have to do with the failure of -XRay-Lithography- EUV (now called Extreme UV) to provide fast enough exposures despite decades of development and billions in research investment. This is a hard problem, but quadruple patterning is also nasty and expensive at 7nm. Even if you can identify the error... if you can't make almost every one of a couple billion transistors correctly, you can't make a modern CPU.

I'd recommend reading a few recent articles on the topic:

The problem with lithography http://spectrum.ieee.org/semiconductors/devices/leading-chip...

A depressing conclusion https://www.hpcwire.com/2016/07/28/transistors-wont-shrink-b...

An optimistic expert https://www.semiwiki.com/forum/content/6590-scott-jones-iss-...

This could be useful to reverse-engineers who may want to do security verification (are there a hidden backdoors in this chip outside its specifications?) or to simply clone a chip outright.

I'm surprised lithography hasn't been replaced with something more nanoscale in origin like some kind of atomic deposition process where individual atoms are precisely bombarded onto the substrate to build up the features atom by atom.

It would take longer to manufacture each chip, but if the machines to do the deposition were relatively cheap and simple to construct, they're not that far off of electron beams, the result could be a massively parallel manufacturing process.

Current production seems very counterintuitive from a manufacturing/industrial engineering perspective. There are around 9 main processes and only about 3 add material. Depending on the chip design, it's probably going to 500-2000 manufacturing steps. That being said, each silicon wafer can hold up to hundreds of chips, making for a big batch. Going up to 18" wafers would make it even more appealing to stick with current methods of production.

With how expensive all fab machines are, I don't see it becoming economical anytime soon for a complete overhaul of tooling.

"longer" is a bit of an understatement when lithography can sweep across a wafer at centimeters per second with nanometers of precision. Good luck ever finishing a single chip atom by atom.

I'm presuming with the right control you can fire out millions of atoms per second, possibly more if you have multiple "guns". I'm not talking about dropping each into place with some kind of claw.

"Longer" if you're talking atom by atom is an understatement, you're going to almost never finish. Electron beams might be something relevant, but they're already being investigated.

E-beam lithography is a thing, and as with all next-gen litho techniques, it too has its fair share of problems. For example, shot noise is a major problem which means that every time you halve your node, you're going to halve your throughput. This is devastating for semiconductor manufacturing, TSMC is already working double shifts trying to match demand.

Also, the important thing to realize about semiconductors is that demonstrating something in the lab is a relatively easy ordeal, but making it mass manufacturable in a timely fashion with good yields is a herculean task. You can actually use X-ray litho for something more "nanoscale in origin" but it's really, REALLY difficult to make it in production.

> You can actually use X-ray litho

Wouldn't that result in a threshold shift? (X-rays are well beyond Si02 bandgap, so you'd get electron-hole pairs in the oxide. The electrons are fairly mobile, but the holes get trapped iirc.)

It still takes weeks to months to manufacture chips using the current process, so the time budget is there.

> Essentially, it takes a very long time to obtain each pattern, and you need a lot of patterns. By the time you've finished imaging, management has brought you your golden watch.

What does this last part about the golden watch mean? Is it a reference to retirement?

Some companies gave out wristwatches commemorating significant tenures. There's even a Domino's Rolex.

Pardon my ignorance, but would it be possible to use X-rays to read the contents of memory? Say, in a TPM or Secure Enclave? I feel like if you had an accurate enough beam you could detect if a memory cell is "charged" or not.

I'm not sure about whether you can do that with x-rays, however you might find this paper interesting - 'Reverse engineering Flash EEPROM memories using Scanning Electron Microscopy' - http://www.cl.cam.ac.uk/~sps32/cardis2016_sem.pdf

Thank you for that relevant article and interesting read. I don't know why you're being downvoted, but I did my part to restore the balance.

X-rays are ionizing radiation. You would just corrupt the fuck out of the memory.

I'm far from an expert on the subject but as far as I know you can only see the structure of the chip (how the transistors are wired together, basically), not the current state of the logic. So you can use this to dump a hardwired ROM but not dynamic content.

This isn't exactly what you asked for, but you might be interested in it anyway.

https://arstechnica.com/gadgets/2013/02/ice-type-attacks-giv...

It's an article about a paper published in Nature about X-Ray tomography to image nm-scale features in modern ICs.

And the only image presented in the whole article is a completely unrelated Chipworks die shot at about 10um per pixel.

Wouldn't this method also erase any EEPROMs on the die?

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