Could asynchronous designs improve performance of future CPUs if and when Moore's Law hits physical limits?
A clock is a signal that is used as a valid signal for the data moving across a bus. That could be as short as between pipeline stages.
With async you have a different valid signal, which you will need to derive.
With aggressive dynamic frequency and voltage scaling, clock gating, power gating and having different power and clock islands you get a design that is very difficult to improve on. What AMD has done recently with circuits that lower voltage based on reading the environment on chip rather than sticking to a frequency: voltage mapping is a nice optimisation.
What async designs don't improve on are all the static power issues that are increasingly important.
It all adds up to being an interesting take on the problem of digital design, but not much more.
It already did. Sophie Wilson said [0] its 28nm for ever. Scaling further makes no economic sense (unless you really need the space, e.g. in Smartphones).
That's not quite what her slide said. It's that the transistors on 14nm are _currently_ more expensive than those at 28nm, although that may change.
And then she states that only some things will make sense to do at less than 28nm. But a lot of the really big players are already at 14nm or will be there very shortly. Apple, Intel, Samsung, AMD and Nvidia are at 14nm now, either for their newest products or ones to be introduced later this year.