AMD Ryzen Full Lineup Prices, Specs and Clock Speeds Leaked

What does this mean? That it will only support booting from a NVMe device if it is plugged in to one particular PCIe port?

Getting an Intel Xeon E3 for socket 1151 isn't particularly hard or expensive either.

That's not correct. All 6th Gen Core i3 have ECC support, and the 7th Gen Core i3 that have 'E' in the product name support ECC:

http://ark.intel.com/products/97130/Intel-Core-i3-7101E-Proc...

That said if you want hardware level attacks then attacks against the cachelines of the CPU are considerably more dangerous and reliable and there is very little one can do to mitigate against those.

On some systems, ECC is flat out broken or silently ignored. On many others ECC errors aren't reported to the OS in granular enough batches to do anything about them.

Edit: relevant portions:

> Before we begin to discuss our results, we must first discuss ECC protected systems and the fact that there are no standards on what constitutes ECC protection or ECC event reporting. At its base level, ECC protection simply means that a server can handle or correct single bit errors, although some systems advertise the ability to correct multiple bit errors. Generally, it is our belief that ECC events should be reported to the operating system so that savvy users can gauge the health of their infrastructure.

> Unfortunately, server vendors routinely use a technique called ECC threshold or the 'leaky bucket' algorithm where they count ECC errors for a period of time and report them only if they reach certain levels of failure. From what we understand, this threshold is commonly above 100 per hour, but this remains a trade secret and varies based on the server vendor. So, to see ECC errors (MCE in Linux or WHEA in Windows), there generally needs to be 100 bit flips per hour or greater. This makes “seeing” Rowhammer on server error logs more difficult.

> In addition, we have observed some server vendors will NEVER report ECC events back to the OS, although they might get logged into IPMI. Typically, users expect to see correctable ECC errors logged directly to the OS or that halt the system when they cannot be corrected. During our investigation into this phenomenon, we even encountered one server that neither reported ECC events to the OS nor halted when bit flips were not correctable. The end result was data corruption at the application level. This is something, in our opinion, that should never happen on an ECC protected server system.

> ...

> Using these advanced techniques, we were able to observe ECC events within the first 3 minutes of test time. Generally, this system would lockup or reboot within 30 minutes. Once again, this was on a Rowhammer mitigated system using both ECC and double refresh. So it follows that dual mitigations, on some systems, appear to be flawed and can be exploited as a denial of service.

It's important but it's not that important outside of specific applications/use cases.

AMD and Intel engineers have hardware quite early to work on this, long before the consumer product ships.

However if you only have one nvidia gpu (and have a different kind of gpu for display), then I think simply running "sudo rmmod vfio" "sudo modprobe nvidia" would work.

Maybe we had different setups, so this wouldn’t apply – I used to unbind the device with the following script, and then load the `nvidia` module; the device was then available on the host:

  for dev in "0000:01:00.0" "0000:01:00.1"; do
          if [ -e /sys/bus/pci/devices/${dev}/driver ]; then
                  echo "${dev}" > /sys/bus/pci/devices/${dev}/driver/unbind
          fi
  done

Once Raven Ridge will be out we can discuss it, currently Summit Ridge is nearly unknown.