We're 2017, VHDL 2008 was released 9 years ago, and this book is using VHDL 93.
A raeson for this is that we have so many tools and the subset we can use the the GCD of all parsers in all tools.
Linter, EC-checker, simulator (at least one, often more than one), planner, synthesis/build tool, integration tool etc.
The synthesis subset of Verilog 2001 and 2005 are as far as I have seen accepted by virtually all tools. I tend to err on the side of caution and use Verilog 2001.
Luckily I read [1] and realized that VHDL can be written in a better way, even with old toolchains. This 2proc style is so much easier to debug than typical RTL syle. It was unfortunate that the 2010 era Quartus II toolchain did not optimize my behavioral code well. The CPU caches were the worst offenders, which isn't too surprising. Tons of enormous, almost certainly inefficient, muxes really pushed the LE limits on the FPGA and my patience during the very long synthesis time.
[0]: https://github.com/jevinskie/mips--/tree/master/project4/sou...