Mcasm – A Microcode Assembler
bedroomlan.org
bedroomlan.org
This is an example of the syntax it has. https://github.com/hansihe/ttl_cpu/blob/master/microcode/mic...
It, along with the assembler is configured through a yaml file. https://github.com/hansihe/ttl_cpu/blob/master/microcode/map...
If anyone is interested, there is an unfinished article about the project located here. http://hansihe.com/2016/11/25/i-built-a-computer-from-scratc...
> If anyone is interested in seeing articles on those things as well, please tell me.
To which I'd like to respond: "Oh very much so! Please share!"
I've subscribed to your RSS feed, so you're sure to have at least one very interested reader.
But here's another idea, if you live close to a university that teaches semiconductor physics or chip design check with them, the system I worked on was used by graduate students and for general research...
I don't think any fab will talk to you. A "real" chip is usually millions of dollars even for older processes.
If you don't care about the actual fabrication then you can use programmable logic like FPGA and get something very close to an actual chip design running on an actual chip. You can probably just get a design to run in a simulator ...
Been a long time since I looked at it. No idea if they have a packaging option.
Why? I do chip design for a living, and I much prefer to work with an FPGA. They are "real silicon" as much as an ASIC.
"Because" is a perfectly good answer, btw.
For prototyping, ams 0.35u process has been quite affordable at 650 euro/mm^2.
That's probably just about feasible, but if you want it to actually work you'll need to be or find the services of someone very familiar with the design process.
(My own design experience is a tiny corner of a Dialog Semi chip. I don't think you can do this kind of thing on your own, but with the right startup team and market you might be able to crowdfund it.)
You cannot just throw some Verilog at the fab and get silicon back. You need to use some very expensive software that generates and validates the actual format they need. Hence you would go through a third-party company that specialises in taking your Verilog and does the work needed to get it to the point that the fab can make it.
1. http://www.clifford.at/yosys/ 2. http://opencircuitdesign.com/qflow/