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Comment by notforgot | Hacker News Reader

Can I write an ASIC with it?

Yes you can!

(no idea why emddudley is claiming otherwise)

I was under the impression you could too. Can you somehow convert it to a format say Magic VLSI could open, out of curiosity.

Magic is a layout tool - you need to synthesize your HDL (Verilog and/or VHDL), then map it to the technology you are trying to target.

In short, not directly - it's the front end tool, and Magic is a different front end tool (direct, full custom layout).

You can design an ASIC with HDL before it is produced but ASIC is not programmable. An ASIC is produced as it is. So you CAN'T WRITE an ASIC.

See Introduction to ASIC Design for a detailed description:

  https://www.u-cursos.cl/ingenieria/2010/2/EL653/1/material_docente/bajar?id_material=305352

No, because VHDL is used for configuring FPGAs. An ASIC is a different beast entirely.

Actually yes - the H stands for hardware: that's any kind of digital logic. You just need a different "back end" and then in theory the same model can run on various targets - in fact there is a whole business model around getting a design up and running on an FPGA and then porting it to an ASIC once you can justify the volume.

You can most certainly build ASICs in VHDL. VHDL is not restricted to any target technology. There are (commercial) tools which allow you to synthesise the masks needed for ASIC production from RTL (register transfer level) VHDL code given a cell library for your target technology. See random Google search result [1].

[1] http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lecture...

No it is not entirely different. Don't forget that FPGA is originally made for prototyping an ASIC, and HDL came out to configure digital circuit before FPGA is invented.

Of course an ASIC cannot be made with only HDL, and not sure if it is a correct expression to say 'to write' an ASIC.

VHDL and Verilog are used in pretty much all CPU design.

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