Cute little cpu!
I like the OPR instruction, neat way of handling increment/decrement (DEC by way of NOT and INC). Are ROR and ROL also chained? That's neat too.
In reality, I've considered switching to a regular mapping, so to have 32 no-operand instructions instead, which would fit the original five operations, all sensible combinations, plus more.
But chaining operands is definitely a more extravagant thing, so I think it can be instructive in showing how creative a solution can be in face of limitations .
[1] http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-h...