Comment by astrodust | Hacker News Reader

Comment by astrodust | Hacker News Reader

DRAM type memory uses a completely different process than flash even if they're both a form of "memory". The performance of DDR-type memory is well beyond anything in the Flash world.

Today 2GB/s is considered very good for an SSD but that would be brutally slow for system memory. DDR4 memory is typically 30-60GB/s per bank with the low end being two-channel, the high end being four.

DRAM has also been the subject of aggressive research and development for many, many decades while large-scale production of flash is a relatively recent phenomenon. It's the widespread adoption of smart phones, thinner notebooks, and ubiquitous USB keychain type devices that as pushed it to the volumes it's at now.

There's also the concern that DDR memory must have a very high level of data integrity, bit-flip errors are severely problematic, and it can't wear out even after trillions of cycles. Flash has more pervasive error correction, and while wear is a minor concern, it's still possible to exhaust it if you really, really try.

I'd say the reason flash memory prices are steeply down is the new "3D" process used by Intel and Samsung has been a big game-changer, allowing for much higher density. DRAM has seen more gradual evolution through the last few generations.

> There's also the concern that DDR memory must have a very high level of data integrity, bit-flip errors are severely problematic, and it can't wear out even after trillions of cycles. Flash has more pervasive error correction, and while wear is a minor concern, it's still possible to exhaust it if you really, really try.

The reason why we can't do the pervasive and extremely aggressive error correction [1] that is used in flash storage to increase usable densities with DRAM is that forward error correction (FEC) is based on blocks, so to read a couple bytes from a block you will have to read the entire block [2], decode it and then you can have your bytes.

This does not work well for RAM ®

Memory fetching is fundamentally based on cache lines; but the overhead in both bandwidth and latency(!) to fetch-and-decode, say, 64K instead of 64 bytes would be completely unacceptable in most applications.

[1] It's one of the major factors contributing to device endurance. [2] Simplification: Practical FEC is multi-tiered, ie. there are different block sizes involved and multiple layers of EC at these block sizes.

I think you're only half-right here.

You cannot do this kind of error correction it like ECC checking in the CPU because it would require multiple clocks or too many pins.

You cannot do this kind of error correction across multiple DRAM chips on board because it would require too many pins.

But you could do this kind of error correction on-chip because you could just read 1024 bits (or more) in parallel from multiple areas (or even mutliple stacked silicon slices).

One problem, however, is that each small read would induce a high energy cost due to the many bits fed into the extensive error correction circuitry. While it shouldn't be a problem for consecutive reads, random-access would indeed lead to a high power consumption which in most cases would not be acceptable.

While your technological reasoning is valid, it explains a factor of price difference but not a change of the difference which is the original question.

The "3D" process explains an additional factor coming into play at recent times. I bet there are a range of technologies which were developed for flash and used for flash manufacturing but not for DRAM manufacturing. This explains a growing disparity between the size/price ratio.

Let's not stop there. If those technologies are useful for flash, why are they not used for DRAM?

I see not hard reason why the 3D process cannot be made useable for DRAM.

The answer, I guess, is that the market forces lead to different priorities where the size/price ratio for DRAM is not so important and more development is done in other areas like speed, reliability, power consumption. So the real reason is not technological but market driven.

DRAM is not flash, flash is not DRAM. They are fundamentally different technologies.

"Let's not stop there. If these technologies are useful for flash, why are they not used for magnetic core memory?"

It's like saying that.

Often pricing is strongly tied to volume. If they're making more flash memory, flash memory becomes less expensive. That does have a moderate cross-over effect into DRAM, anything that drives process improvements benefits all fabricators, but it's not as direct as you'd think.

Reply on news.ycombinator.com