There's no guarantee that an arbitrary C/C++ task will map well onto/into FPGA. Ideally there should be a large number of subtasks that work in parallel with the end result that the overall pipeline (for lack of a better word) is shallow. FPGA clocks aren't fast - order of magnitude slower than CPU - but you can have a lot of simultaneous balls in the air.

Definitely there should be a purely software model, long before you start thinking about Verilog/VHDL and the actual hardware devices to fit them into.

I don't think the developer needs trading experience, especially if a high level model already exists. It should be a well-defined and testable black box.