It has a number of implementations, both fully open source ones (BSD licensed), and proprietary. This one is based on the open source Rocket Chip implementation (https://github.com/ucb-bar/rocket), which is a simple in-order design, something like ARM Cortex-M or Intel Atom. (There is also one open source out-of-order design called BOOM - https://github.com/ucb-bar/riscv-boom)
It's not in my hands personally, but they seem to be over the vapor hump.
I found it an exciting enough product to drop $60 on, anyway.
The performance of MIPS, which it is closest to, has never really been considered anything more than "acceptable". It loses to ARM (which isn't so RISC-y anyway) and x86, so I expect RISC-V to be about the same:
https://www.extremetech.com/extreme/188396-the-final-isa-sho...
http://www.extremetech.com/wp-content/uploads/2014/08/Averag...
Compared to an 8-bit AVR in an Arduino it's definitely much faster, but compared to other 32-bit architectures, it is not.
Hardware has, in addition to the GPIO, UART and ADC/DAC that you're used to from Atmel, a USB 2.0 device controller (it says "OTG", which implies a host controller too, but sometimes people get this mixed up), a SD/MMC/eMMC controller for storage (no idea about SDIO) and gigabit ethernet.
I'm a little disappointed in the lack of wireless connectivity on the SoC, though I suppose you can make up for that with off the shelf USB devices (or a UART bluetooth radio).
You can probably get it to work with a lot of effort and optimisation, but there'll be very little room to do anything with it afterwards.
Afaik AC97 chips run at around 24MHz, are dedicated to the job, and even they stop at 20 bit resolution and sticking the data onto a data bus. Getting better than that is "hard", which is why all the manufacturers pretty much standardised around such a low standard.
However, while most Cortex-M chips have an I2S peripheral to integrate with an external DAC, the HiFive1 doesn't, which might cause some difficulties. Audio out can be implemented with the PWM peripheral, though.
24MHz is "enough" for 20 bits@96kHz ADC and some post processing.
But 20 bits@96kHz is not decent.
For reasonable SNR, you need at least 24 bits, and even then "the experts" offload to an external CPU http://www.tested.com/tech/pcs/454839-tested-why-high-end-pc...
For signal (less audio are more "controller") with high precision you need micro controllers with the power of at least an early 2000s PC (several hundred MHz and single cycle mul/div).
Raspberry Pi 3 is close, but it needs an external ADC/DAC.
Secondly, even if you did want to process at 96kHz, you'd have plenty of CPU left to do so. It's only 2x as intensive as 48kHz (this is a 32 bit CPU so using 16 bit vs 32 bit math is mostly the same, sans DSP instructions) and that amount of headroom is likely available, for example: https://www.rockbox.org/wiki/CodecPerformanceComparison
Thirdly, the article you linked talks about high end DACs but says nothing about the DSP on the card, other than that it has one, for doing... something (?)
Firstly, getting from uncompressed at the input to compressed is basic processing.
Seriously, you don't. Non risk instructions often take Multiple cycles, so you can only do a tiny number of them between samples, usually just enough to compress it to fit the bus speed without loss. https://en.m.wikipedia.org/wiki/Cycles_per_instruction
Thirdly, clearly you didn't rtfa.
Fourthly, go disagree on the teensy forum. https://forum.pjrc.com/threads/27364-Teensy-3-1-and-ADC-FIR-...
Radio signals below 50 kHz are capable of penetrating ocean depths to approximately 200 metres, the longer the wavelength, the deeper. The British, German, Indian, Russian, Swedish, United States [3] and possibly other navies communicate with submarines on these frequencies.
->That requires min 100khz sample rate.