SiFive open sources RISC-V chips

Quake was targeted on a CISC-design general purpose CPU, on a very different process from modern ones. Those factors likely explain much of the difference in clock speed. They just couldn't make 320MHz parts as easily then. Even modern x86 CPUs are RISC inside and have microcode to execute the CISC instructions.

These particular RISC-V parts are targeting the microcontroller marketplace where there's little RAM required.

It's a common configuration for a microcontroller. You're not going to be rendering graphics on a machine like this; you're going to be spending most of the time asleep, to save power and extend battery life, with occasional quick bursts of interrupt-triggered activity which mostly consist of interacting with peripherals. You generally run the processor at a high clock rate because you're trying to get back to sleep as soon as possible, not because you're actually doing anything computationally intensive.

Software for a device like this typically relies heavily on statically-allocated data structures, with limited use of the stack and no dynamic memory allocation at all. It's therefore generally easy to figure out how much RAM you actually need and fit your data structures efficiently into whatever's available. You're not going to be running threads with independent stacks or trying to keep a lot of heap space open to avoid fragmentation; you're just going to use static vars and fixed-length arrays, and the compiler will pack it all in for you.