What really astonishes me though is how you can have these really nice machines and Apple doesn't bother to update the Mac mini. Seriously, an Apple version of this would be a nice desktop.
What really astonishes me though is how you can have these really nice machines and Apple doesn't bother to update the Mac mini. Seriously, an Apple version of this would be a nice desktop.
It would almost have been better if they didn't update it. The 2012 mini was fantastic; you could take it to a quad i7 and 16GB for under $1000 thanks to user-accessible RAM. For most purposes that's much better than the current $1000 mini.
I've been waiting for someone to offer me ECC in a small form factor. This is the first time I've ever seen it.
And that's for embedded microcontrollers and RAM that aren't nearly pushing it to extremely small processes.
Let me just quote IEC 61508, where "FIT" means 10e-9 h:
Causes of soft errors are: (1) Alpha particles from package decay, (2)
Neutrons, (3) external EMI noise, (4) Internal cross-talk. External EMI noise is covered by other requirements of
this international standard.
A soft error occurs when a radiation event causes enough of a charge disturbance to reverse or flip the data state
of a low energized semiconductor memory cell, register, latch, or flip-flop. The error is called “soft” because the
circuit itself is not permanently damaged by the radiation. Soft-errors are classified in Single Bit Upsets (SBU) or
Single Event Upsets (SEU) and Multi-Bit Upsets (MBU).
The soft error rate has been reported (see a) and i) below) to be in a range of 700 Fit/MBit to 1 200 Fit/MBit for
(embedded) memories. This is a reference value to be compared with data coming from the silicon process with
which the device is implemented. Until recently SBU were considered to be dominant, but the latest forecast (see
a) below) reports a growing percentage of MBU of the overall soft-error rate (SER) for technologies from 65 nm
down.
The following literature and sources give details about soft-errors:
a) Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130 nm SRAM. J-L. Autran,
P. Roche, C. Sudre et al. Nuclear Science, IEEE Transactions on Volume 54, Issue 4, Aug. 2007
Page(s):1002 - 1009
b) Radiation-Induced Soft Errors in Advanced Semiconductor Technologies, Robert C. Baumann, Fellow,
IEEE, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005
c) Soft errors' impact on system reliability, Ritesh Mastipuram and Edwin C Wee,
Cypress Semiconductor, 2004
d) Trends And Challenges In VLSI Circuit Reliability, C. Costantinescu, Intel, 2003, IEEE Computer Society
e) Basic mechanisms and modeling of single-event upset in digital microelectronics, P. E. Dodd and L. W.
Massengill, IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583–602, Jun. 2003.
f) Destructive single-event effects in semiconductor devices and ICs, F. W. Sexton, IEEE Trans. Nucl. Sci.,
vol. 50, no. 3, pp. 603–621, Jun. 2003.
g) Coming Challenges in Microarchitecture and Architecture, Ronen, Mendelson, Proceedings of the IEEE,
Volume 89, Issue 3, Mar 2001 Page(s):325 – 340
h) Scaling and Technology Issues for Soft Error Rates, A Johnston, 4th Annual Research Conference on
Reliability Stanford University, October 2000
i) International Technology Roadmap for Semiconductors (ITRS), several papers.I am worried about my personal backups now.
But take 16GB. With 1000 FIT you get pretty much \pi events in one day.
Of course if you don't have ECC memory you don't know that your memory is being silently corrupted. For some people they don't care, for me, I do.
Reading this I thought the best I could do is to believe that workstation with ECC modules and Xeon will have functioning ECC:
"Unfortunately, we have found that there is no consistent, conclusive way to determine if ECC RAM is working properly. ...We've actually asked Intel, Kingston and Asus over the years for their recommendations for methods to confirm that ECC is working, but we haven't gotten much more back than a blank stare."
https://www.pugetsystems.com/labs/articles/How-to-Check-ECC-...
I'm surprised the board/bios manufacturer couldn't answer the question, it's a pretty straight forward system.
[1] They show up as 'SBE' events (single bit error). An 'MBE' event (detectable but not correctable) would presumably result in an unhandled machine check and cause the kernel to reboot.
You can cause bit errors with a hair dryer and see if Linux recognizes them: http://bluesmoke.sourceforge.net/heat_gun.html
You'll find less smoldering, better smell, and less pain if you use an actual hair dryer to dry your hair (rather than a heat gun, which the page is about).
That said, if a bit flips in the wrong place in RAM, even a checksumming file system will not protect you. The file system will happily write out the corrupted data if the checksum is calculated after the bit flip occurs.
http://serverfault.com/questions/674214/what-is-the-rowhamme... adds "ECC effectively turns the Row Hammer exploit into a DOS attack. 1bit errors will be corrected by ECC, and as soon as a non-correctable 2bit error is detected the system will halt (assuming SECDED ECC)."
IMHO there is indeed a great deal of pent-up demand for more powerful Mac Minis. I really wish Apple wouldn't just treat them as incidental devices, but presumably there's not much incentive from their perspective since these are lower margin than their other offerings.
It would compete with the IMac then, and with their notebooks too. Maybe Apple should charge enough of a premium for the mini to justify that loss.
>> It would compete with the IMac then, and with their notebooks too.
Companies that try to avoid competing with themselves often fail quickly and spectacularly (after this approach appearing to work well for an extended time).