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Comment by hga | Hacker News Reader

Hmmm, not really a good article:

To get about the same clock, you need to pay $325.

The Core-i7 980X is made on a smaller process node, 32 instead of 45 nm. The two processors aren't easily compared, the cores in the Core have half the L2 cache of the Phenom (256 vs. 512KB) and the shared L3 is twice as big (12 vs. 6MB).

As for the pricing, according to Wikipedia there's just this one unlocked Core desktop part, vs. a couple of dozen Xeon server parts and 8 4 core dual processor parts. It sure looks like to me like Intel is selling all the server parts it can and is throwing out this one desktop version for the enthusiasts with a price to match.

Anyone have an idea of what the different L2 and L3 cache tradeoffs will mean in practice?

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For the intel the L2 cache (and the L1 of course) are shared for both the hyperthreads, so each hyperthread would get even less than 256K. On AMD, however each thread gets the full 512K. The L3 latency is much larger than the L2 (~40 cycles IIRC) so the smaller L2 would limit the performance of a cache hungry (but not too hungry: see next paragraph) application.

One place where the larger L3 is a win is on low parallelism, memory hungry loads -- they have a much larger L3 all to themselves.

You can't compare Xeons to Phenoms, you need to be looking at Opterons for that. AMD recently released their 12-core Opterons (4 different models) and they have 3 8-core and 5 6-core Opterons as well (9 if you distinguish between 2-socket and 8-Socket versions).

I'm only comparing them as a business decision WRT allocating fab lines. I'm assuming the profit margins are higher on server chips and the high end enthusiast desktop ones and proposing this as an explanation for Intel's product mix. There's got to be some reasons Intel is only selling one model of the latter while selling a couple dozen of the former with this microarchitecture and on this process node.

Speaking generally, more cache is better. Most workloads will like an extra 6MB in the L3 more than an extra 1.5MB (total) in the L2.

Speaking generally, lower latency to main memory is better than more cache.

On a generation of one platform I dealt with, main memory latency and bandwidth (faster processor design, on-board memory controller, RDRAM) were on par with the L3 cache from the previous platform generation.

The cache shrank, and the performance increased.

All true, but that's not what hga asked :-)

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