Initial patches to add an MC layer for RISC-V | Hacker News Reader

Initial patches to add an MC layer for RISC-V

llvm.org

31 pointscokernel_hacker14 comments

Open articleView on HN

The author of these patches is giving a talk at the LLVM dev meeting on Thursday:

https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/Yp...

For those confused by the title, it means they're working on adding LLVM support for RISC-V.

What's an MC layer?

It is the low-level assembler-related machinery in LLVM.

For more details, see http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html

Thank you. Guessing the MC stands for 'Machine Code' then.

When this is done, does it mean any LLVM language can compile to RISC-V? Or is there additional per-language work that would need to happen first?

There'll be some small amount of additional per-language work generally. I (and lowrisc.org as a whole) would be keen to support people attempting such ports. Rust and Swift are obviously high on the list.

So they have an LLVM target for RISC-V. They could submit that but they choose to divide it up into pieces and submit them piecemeal. This is the first piece of that meal. If you want to skip to the dessert:

https://github.com/riscv/riscv-llvm

> They could submit that but they choose to divide it up into pieces and submit them piecemeal

It's common practice in OSS to request splitting of large patches into smaller as-much-self-contained-as-possible pieces, to make reviewing more feasible. Same goes for non-OSS products in companies with good development practices, I guess.

It's actually a reimplementation, because there were some (I think legal) problems with the implementation that you linked

Thanks. That sounds similar to the GCC kerfuffle.

Please see here for background on the effort: http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748....

I believe that given RISC-V's status as a clean and open ISA, the RISC-V port for any project should be the most accessible, best documented and cleanest. I am attempting to pursue this for the LLVM port. This has real practical benefit - the easier it is for research groups and hobbyists to hack on the RISC-V LLVM backend, the easier it is to perform interesting hardware/software co-design and architectural research.

When will GCC get their RISC-V support? I thought I read the UCB lawyer issue got resolved. Or is that not so?

RISC-V has GCC support already:

https://github.com/riscv/riscv-gcc

But the UCB IP lawyers are preventing it (for now) from getting upstreamed to GCC proper:

http://www.phoronix.com/scan.php?page=news_item&px=GCC-RISCV...

Reply on news.ycombinator.com