Intel, TSMC and other chipmakers weigh extreme ultraviolet lithography
spectrum.ieee.org
spectrum.ieee.org
The sales folks don't care - they just sell. History has shown that time and time again, if they promise to deliver, they do - through sheer force of will and money (turns out the Mythical Man Month isn't so mythical if you're really willing to put 30x the amount of cost/people on it as is technically necessary). So when the researchers said they thought they could pull EUV off, the sales guys went ahead and sold it.
And the customers bought it, as you can read in this article. But if ASML can't pull it off, then we'll see a bunch of really interesting changes in the semicon landscape I think. ASML isn't the only company who made the full-on bet on EUV. If ASML can't deliver, then Intel may have an even bigger problem than ASML. I'm really curious what would happen then, almost to the point of hoping EUV will catastrophically fail.
ASML has no believable competition in this space.
There are a bunch of other roads that have been popping up recently IIUC.
I had hope for e-beam lithography, which works fine and has been able to get down to similar resolutions for years, but is just too slow for production. No masks, just writing the wafer with a scanning beam under computer control. Writing is one pixel at a time, which is why it's slow.
[1] http://spie.org/newsroom/4493-making-extreme-uv-light-source...
http://spie.org/newsroom/4609-multiple-electron-beam-direct-...
I know the article you linked lists the many issues that arise, but to even try such a technique- I think it demonstrates just how hard the problem of further photolithography improvement is.
Very soft x-rays/EUV is amongst the hardest regions in which to work as the photons are just the right energy to be strongly absorbed by most materials, so as the article states, losses to the optics are significant, i.e. you lose ~half your photons in every mirror.
http://digbib.ubka.uni-karlsruhe.de/volltexte/fzk/6606/6606....
Unsurprisingly, synchrotron sources produce too much out of band radiation so heat load on the optics is high, which is not so good for fragile EUV optics that need to last a long time.
As background: EUV lithography requires high power in a narrow bandpass. 250 watts of power at 13.5 nm (92 eV) with a <2% bandpass is a really tough task when you think about it. Synchrotrons fundamentally produce full spectrum radiation, and parameters of the storage ring are varied to get the desired energy distribution. Typically you then throw away all the photons other than the ones you are interested in (turning waste photons into heat), and the inherent brightness of the synchrotron source still leaves you lots of photons in your bandpass of interest. Heat loads on front end optics on insertion device beamlines at high energy storage rings like SPring-8 are hundreds of watts per square mm. cf. the power dissipation of your CPU at a few square mm die size and <100 watts power.
See also: https://pure.tue.nl/ws/files/3872978/banine2014.pdf
A fall-back scenario, should the tin-vaporizing method fail to deliver, was the use of a Free Electron Laser, which can produce a huge range of wavelengths directly. However, since compact FEL's are not really feasible, this would mean a single source for an entire fab, with complex infrastructure required to distribute the EUV light to multiple scanners. Far from ideal.
Couldn't this process be sped up by multiplying the number of scanning beams in operation at any one time?
Could you not use a Halbach array?
https://en.m.wikipedia.org/wiki/Halbach_array
Furthermore, I had in mind that you'd have synchronisation between the beams. Consider the use case of one e-beam per chip. As each wafer has multiple chips you would still have plenty of room for parallel beams working at any one time.
As for cost, do you have a ballpark figure for how much the devices cost?
On a less fanboy note - I'd have loved to see a more detailed description of how they ship the EUV tools. I can only imagine the logistical headache involved for Intel - they spec out all of their fabs to be identical for quality reasons. Shipping nine school-bus-sized, vacuum sealed containers to some far corner of the globe has to be a shitload of work. And then you have to set it up when it finally gets there! In vacuum! And then when you're done, you have to do it again for each Intel fab!
(Fanboy rant over now, I swear, I just get really excited about making all these miniscule things for some reason.)
Intel has 'the best' chips because they literally pay the price for being, at least on their headline grabbing products, a full process generation ahead of more or less the entire rest of the semiconductor industry.
I think they've acknowledged that they're slowing down with their new strategy [1].
[1] http://arstechnica.com/information-technology/2016/03/intel-...
They've already decided they're going to fab ARM chips, so I think they've already come to this conclusion.
The plot 2/3 down the page compares Intel's process with competitors. It's a bit out of date in the sense that it only shows projections instead of the result after-the-fact, but the plot shows that Intel is still ahead.
Took a long time for physics to start to get in the way.
This video has a little bit of the tool assembly and support systems: https://www.youtube.com/watch?v=ttbaaI5xUcg
The logistical headache is not the problem of Intel, but for ASML. A downtime costs around ten thousand euros per hour and can run up in the millions. Distribution of spare parts is very important.
How will the future be different?
If a wall is hit, the companies that /make/ the equipment will still need to sell units to someone, so the market equilibrium will push them closer and closer to the source cost for the (very often small batch/one off) parts. The race then between the rate they need/want to produce units to stay in business, and how long those in the market can defer purchasing new units.
There's no longer plenty of room at the bottom. Atoms are too big and the speed of light is too slow.
If you haven't heard of the Mill CPU, it's one example of completely rethinking things: http://millcomputing.com/docs/belt/ Of course, the problem there is the missing software/OS toolchain. But it also points towards there being some huge inefficiencies present in "classic" von Neumann architectures, and to me, the possibility that there's still room for things to improve.
This is actually the direction AMD is going with Navi, not because of the performance gains per se but because it helps yields big time. You can pre-bin your chips, then stitch a bunch of small chips into medium chips while keeping your yields high.
In theory you can scale up for quite a while. At the long term, you will eventually be limited by clock degradation/signal propagation time however.
The short-term problem is heat and power. This doesn't help efficiency gains per se. If you are stitching together four 600mm^2 dies then you are going to be pulling 1000-1200W and dumping that back out into your cooling system. For US consumers, their circuit breakers are a much more immediate limit. Most household circuits are 15A @ 120V, and that's an instantaneous limit. You are not supposed to continuously pull more than 80% of a circuit's instantaneous rating, so that's 12A (1440W at the wall). Factor in the losses from the PSU's 80% efficiency and you are now talking 1152W continuously. Again, that works out to about four 600mm^2 GPU dies, plus some power budget for the CPU and so on. And you'd probably need to take drastic measures to keep that cool - that's a lot of heat in a small surface area.
Of course but notice that your desktop computer is using an x86 ISA instead of a RISC ISA because in many case backward compatibility and network effect trump performance improvement..
Because saying "We're using x-rays" just sounds too scary right now...
Getting rid of two mirrors would double the energy at waver, removing 6 mirrors increases it by a factor of ten.