5th RISC-V Workshop Preliminary Agenda

Very excited to see the V extension is already in a proposal-quality draft. It's the last big piece separating RISC-V from data-heavy consumer and server workloads.

>> Very excited to see the V extension is already in a proposal-quality draft...

And Go on RISC-V, and a JVM, and video decode instructions, and security work, VM work, thousand core concepts, dev boards, multiple hardware implementations, better simulators, and all the rest. This shit is getting real very quickly.

Any more details available on this SiFive development board?

By the numbering, it seems like it would be one of their embedded form-factor platforms as a dev board. https://www.sifive.com/products/freedom/

I wonder if it will be FPGA based or use an ASIC. Also if it will have a block device and network, which are the drawbacks of the current platform.

It wouldn't be that hard to have a network interface for the FPGA implementations. The Zynq SoCs have two network interfaces, though most dev boards only connect one of them to a connector.

RISC-V has serious momentum.